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RTL code of an 8-bit CPU designed in Verilog with a separate file for each module.

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Haaris-RTL/8-bit-CPU

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This is a personal project where I design an 8-bit CPU with an ALU capable of performing basic mathematical operations, essentially making it a calculator.

I am designing each module separately and they will be uploaded as I make progress on them. This includes Verilog design and testbench code files.

The intention of this project is to have a working design that can be programmed onto an FPGA provided it has the right I/O.

This project was inspired by Ben Eater's 8-bit breadboard CPU which you can look at here (https://eater.net/8bit).