Project name

• This is a cpu implemented in systemVerilog
• The project is the final target for Computer composition class of Department of Computer science in Tongji Univerity

Running environment

• Vivado 2016.2
• ModelSim PE 10.4c

Attention

• My code is totally rubbish, but it will indeed help you pass the online test.
• Change names of REGISTER, and it can change the timming log thoroughly

Update

• update on July 27th in 2018