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added generic version of Ascon V1.1 for our interface
added CAESAR API generic Ascon V1.1 variant
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138 changes: 69 additions & 69 deletions
138
HDL/ascon_128_xlow_area/ascon_counter.vhdl → ...v1/ascon_128_xlow_area/ascon_counter.vhdl
100755 → 100644
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -1,69 +1,69 @@ | ||
| ------------------------------------------------------------------------------- | ||
| -- Title : Ascon Counter | ||
| -- Project : | ||
| ------------------------------------------------------------------------------- | ||
| -- File : ascon_counter.vhdl | ||
| -- Author : Hannes Gross <hannes.gross@iaik.tugraz.at> | ||
| -- Company : | ||
| -- Created : 2014-05-20 | ||
| -- Last update: 2014-05-26 | ||
| -- Platform : | ||
| -- Standard : VHDL'93/02 | ||
| ------------------------------------------------------------------------------- | ||
| -- Description: | ||
| ------------------------------------------------------------------------------- | ||
| -- Copyright 2014 Graz University of Technology | ||
| -- | ||
| -- Licensed under the Apache License, Version 2.0 (the "License"); | ||
| -- you may not use this file except in compliance with the License. | ||
| -- You may obtain a copy of the License at | ||
| -- | ||
| -- http://www.apache.org/licenses/LICENSE-2.0 | ||
| -- | ||
| -- Unless required by applicable law or agreed to in writing, software | ||
| -- distributed under the License is distributed on an "AS IS" BASIS, | ||
| -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | ||
| -- See the License for the specific language governing permissions and | ||
| -- limitations under the License. | ||
| ------------------------------------------------------------------------------- | ||
| -- Revisions : | ||
| -- Date Version Author Description | ||
| -- 2014-05-20 1.0 Hannes Gross Created | ||
| ------------------------------------------------------------------------------- | ||
|
|
||
| library ieee; | ||
| use ieee.std_logic_1164.all; | ||
| use ieee.numeric_std.all; | ||
|
|
||
| entity ascon_counter is | ||
|
|
||
| port ( | ||
| ClkxCI : in std_logic; | ||
| RstxRBI : in std_logic; | ||
| CountEnablexSI : in std_logic; | ||
| CounterRoundxDO : out std_logic_vector(3 downto 0); | ||
| CounterFunctSelxDO : out std_logic_vector(2 downto 0); | ||
| CounterSubIterationxDO : out std_logic_vector(5 downto 0)); | ||
|
|
||
| end entity ascon_counter; | ||
|
|
||
| architecture structural of ascon_counter is | ||
| signal CounterxDP : std_logic_vector(12 downto 0); | ||
| begin -- architecture structural | ||
|
|
||
| counter_reg_p: process (ClkxCI, RstxRBI) is | ||
| begin -- process counter_reg_p | ||
| if RstxRBI = '0' then -- asynchronous reset (active low) | ||
| CounterxDP <= (others => '0'); | ||
| elsif ClkxCI'event and ClkxCI = '1' then -- rising clock edge | ||
| if CountEnablexSI = '1' then -- Count enable | ||
| CounterxDP <= std_logic_vector(unsigned(CounterxDP) + 1); | ||
| end if; | ||
| end if; | ||
| end process counter_reg_p; | ||
|
|
||
| CounterRoundxDO <= CounterxDP(12 downto 9); | ||
| CounterFunctSelxDO <= CounterxDP( 8 downto 6); | ||
| CounterSubIterationxDO <= CounterxDP( 5 downto 0); | ||
|
|
||
| end architecture structural; | ||
| ------------------------------------------------------------------------------- | ||
| -- Title : Ascon Counter | ||
| -- Project : | ||
| ------------------------------------------------------------------------------- | ||
| -- File : ascon_counter.vhdl | ||
| -- Author : Hannes Gross <hannes.gross@iaik.tugraz.at> | ||
| -- Company : | ||
| -- Created : 2014-05-20 | ||
| -- Last update: 2014-05-26 | ||
| -- Platform : | ||
| -- Standard : VHDL'93/02 | ||
| ------------------------------------------------------------------------------- | ||
| -- Description: | ||
| ------------------------------------------------------------------------------- | ||
| -- Copyright 2014 Graz University of Technology | ||
| -- | ||
| -- Licensed under the Apache License, Version 2.0 (the "License"); | ||
| -- you may not use this file except in compliance with the License. | ||
| -- You may obtain a copy of the License at | ||
| -- | ||
| -- http://www.apache.org/licenses/LICENSE-2.0 | ||
| -- | ||
| -- Unless required by applicable law or agreed to in writing, software | ||
| -- distributed under the License is distributed on an "AS IS" BASIS, | ||
| -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | ||
| -- See the License for the specific language governing permissions and | ||
| -- limitations under the License. | ||
| ------------------------------------------------------------------------------- | ||
| -- Revisions : | ||
| -- Date Version Author Description | ||
| -- 2014-05-20 1.0 Hannes Gross Created | ||
| ------------------------------------------------------------------------------- | ||
|
|
||
| library ieee; | ||
| use ieee.std_logic_1164.all; | ||
| use ieee.numeric_std.all; | ||
|
|
||
| entity ascon_counter is | ||
|
|
||
| port ( | ||
| ClkxCI : in std_logic; | ||
| RstxRBI : in std_logic; | ||
| CountEnablexSI : in std_logic; | ||
| CounterRoundxDO : out std_logic_vector(3 downto 0); | ||
| CounterFunctSelxDO : out std_logic_vector(2 downto 0); | ||
| CounterSubIterationxDO : out std_logic_vector(5 downto 0)); | ||
|
|
||
| end entity ascon_counter; | ||
|
|
||
| architecture structural of ascon_counter is | ||
| signal CounterxDP : std_logic_vector(12 downto 0); | ||
| begin -- architecture structural | ||
|
|
||
| counter_reg_p: process (ClkxCI, RstxRBI) is | ||
| begin -- process counter_reg_p | ||
| if RstxRBI = '0' then -- asynchronous reset (active low) | ||
| CounterxDP <= (others => '0'); | ||
| elsif ClkxCI'event and ClkxCI = '1' then -- rising clock edge | ||
| if CountEnablexSI = '1' then -- Count enable | ||
| CounterxDP <= std_logic_vector(unsigned(CounterxDP) + 1); | ||
| end if; | ||
| end if; | ||
| end process counter_reg_p; | ||
|
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| CounterRoundxDO <= CounterxDP(12 downto 9); | ||
| CounterFunctSelxDO <= CounterxDP( 8 downto 6); | ||
| CounterSubIterationxDO <= CounterxDP( 5 downto 0); | ||
|
|
||
| end architecture structural; |
154 changes: 77 additions & 77 deletions
154
HDL/ascon_128_xlow_area/ascon_sbox5.vhdl → asconv1/ascon_128_xlow_area/ascon_sbox5.vhdl
100755 → 100644
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -1,77 +1,77 @@ | ||
| ------------------------------------------------------------------------------- | ||
| -- Title : Ascon SBox | ||
| -- Project : | ||
| ------------------------------------------------------------------------------- | ||
| -- File : ascon_sbox5.vhdl | ||
| -- Author : Hannes Gross <hannes.gross@iaik.tugraz.at> | ||
| -- Company : | ||
| -- Created : 2014-05-20 | ||
| -- Last update: 2014-05-23 | ||
| -- Platform : | ||
| -- Standard : VHDL'93/02 | ||
| ------------------------------------------------------------------------------- | ||
| -- Description: | ||
| ------------------------------------------------------------------------------- | ||
| -- Copyright 2014 Graz University of Technology | ||
| -- | ||
| -- Licensed under the Apache License, Version 2.0 (the "License"); | ||
| -- you may not use this file except in compliance with the License. | ||
| -- You may obtain a copy of the License at | ||
| -- | ||
| -- http://www.apache.org/licenses/LICENSE-2.0 | ||
| -- | ||
| -- Unless required by applicable law or agreed to in writing, software | ||
| -- distributed under the License is distributed on an "AS IS" BASIS, | ||
| -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | ||
| -- See the License for the specific language governing permissions and | ||
| -- limitations under the License. | ||
| ------------------------------------------------------------------------------- | ||
| -- Revisions : | ||
| -- Date Version Author Description | ||
| -- 2014-05-20 1.0 Hannes Gross Created | ||
| ------------------------------------------------------------------------------- | ||
|
|
||
| library ieee; | ||
| use ieee.std_logic_1164.all; | ||
| use ieee.numeric_std.all; | ||
|
|
||
| entity ascon_sbox5 is | ||
|
|
||
| port ( | ||
| SboxINxDI : in std_logic_vector(4 downto 0); | ||
| SboxOUTxDO : out std_logic_vector(4 downto 0)); | ||
|
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| end entity ascon_sbox5; | ||
|
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| architecture structural of ascon_sbox5 is | ||
|
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| begin -- architecture structural | ||
|
|
||
| -- purpose: implementation of the Ascno sbox | ||
| -- type : combinational | ||
| sbox: process (SBoxINxDI) is | ||
|
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| -- Temp variables; | ||
| variable SBoxT0xV, SBoxT1xV, SBoxT2xV : std_logic_vector(4 downto 0); | ||
|
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||
| begin -- process sbox | ||
| SBoxT0xV(0) := SBoxINxDI(0) xor SBoxINxDI(4); | ||
| SBoxT0xV(1) := SBoxINxDI(1); | ||
| SBoxT0xV(2) := SBoxINxDI(2) xor SBoxINxDI(1); | ||
| SBoxT0xV(3) := SBoxINxDI(3); | ||
| SBoxT0xV(4) := SBoxINxDI(4) xor SBoxINxDI(3); | ||
|
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| SBoxT1xV(0) := SBoxT0xV(0) xor (not SBoxT0xV(1) and SBoxT0xV(2)); | ||
| SBoxT1xV(1) := SBoxT0xV(1) xor (not SBoxT0xV(2) and SBoxT0xV(3)); | ||
| SBoxT1xV(2) := SBoxT0xV(2) xor (not SBoxT0xV(3) and SBoxT0xV(4)); | ||
| SBoxT1xV(3) := SBoxT0xV(3) xor (not SBoxT0xV(4) and SBoxT0xV(0)); | ||
| SBoxT1xV(4) := SBoxT0xV(4) xor (not SBoxT0xV(0) and SBoxT0xV(1)); | ||
|
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| SboxOUTxDO(0) <= SBoxT1xV(0) xor SBoxT1xV(4); | ||
| SboxOUTxDO(1) <= SBoxT1xV(1) xor SBoxT1xV(0); | ||
| SboxOUTxDO(2) <= not SBoxT1xV(2); | ||
| SboxOUTxDO(3) <= SBoxT1xV(3) xor SBoxT1xV(2); | ||
| SboxOUTxDO(4) <= SBoxT1xV(4); | ||
| end process sbox; | ||
|
|
||
| end architecture structural; | ||
| ------------------------------------------------------------------------------- | ||
| -- Title : Ascon SBox | ||
| -- Project : | ||
| ------------------------------------------------------------------------------- | ||
| -- File : ascon_sbox5.vhdl | ||
| -- Author : Hannes Gross <hannes.gross@iaik.tugraz.at> | ||
| -- Company : | ||
| -- Created : 2014-05-20 | ||
| -- Last update: 2014-05-23 | ||
| -- Platform : | ||
| -- Standard : VHDL'93/02 | ||
| ------------------------------------------------------------------------------- | ||
| -- Description: | ||
| ------------------------------------------------------------------------------- | ||
| -- Copyright 2014 Graz University of Technology | ||
| -- | ||
| -- Licensed under the Apache License, Version 2.0 (the "License"); | ||
| -- you may not use this file except in compliance with the License. | ||
| -- You may obtain a copy of the License at | ||
| -- | ||
| -- http://www.apache.org/licenses/LICENSE-2.0 | ||
| -- | ||
| -- Unless required by applicable law or agreed to in writing, software | ||
| -- distributed under the License is distributed on an "AS IS" BASIS, | ||
| -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | ||
| -- See the License for the specific language governing permissions and | ||
| -- limitations under the License. | ||
| ------------------------------------------------------------------------------- | ||
| -- Revisions : | ||
| -- Date Version Author Description | ||
| -- 2014-05-20 1.0 Hannes Gross Created | ||
| ------------------------------------------------------------------------------- | ||
|
|
||
| library ieee; | ||
| use ieee.std_logic_1164.all; | ||
| use ieee.numeric_std.all; | ||
|
|
||
| entity ascon_sbox5 is | ||
|
|
||
| port ( | ||
| SboxINxDI : in std_logic_vector(4 downto 0); | ||
| SboxOUTxDO : out std_logic_vector(4 downto 0)); | ||
|
|
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| end entity ascon_sbox5; | ||
|
|
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| architecture structural of ascon_sbox5 is | ||
|
|
||
| begin -- architecture structural | ||
|
|
||
| -- purpose: implementation of the Ascno sbox | ||
| -- type : combinational | ||
| sbox: process (SBoxINxDI) is | ||
|
|
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| -- Temp variables; | ||
| variable SBoxT0xV, SBoxT1xV, SBoxT2xV : std_logic_vector(4 downto 0); | ||
|
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| begin -- process sbox | ||
| SBoxT0xV(0) := SBoxINxDI(0) xor SBoxINxDI(4); | ||
| SBoxT0xV(1) := SBoxINxDI(1); | ||
| SBoxT0xV(2) := SBoxINxDI(2) xor SBoxINxDI(1); | ||
| SBoxT0xV(3) := SBoxINxDI(3); | ||
| SBoxT0xV(4) := SBoxINxDI(4) xor SBoxINxDI(3); | ||
|
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| SBoxT1xV(0) := SBoxT0xV(0) xor (not SBoxT0xV(1) and SBoxT0xV(2)); | ||
| SBoxT1xV(1) := SBoxT0xV(1) xor (not SBoxT0xV(2) and SBoxT0xV(3)); | ||
| SBoxT1xV(2) := SBoxT0xV(2) xor (not SBoxT0xV(3) and SBoxT0xV(4)); | ||
| SBoxT1xV(3) := SBoxT0xV(3) xor (not SBoxT0xV(4) and SBoxT0xV(0)); | ||
| SBoxT1xV(4) := SBoxT0xV(4) xor (not SBoxT0xV(0) and SBoxT0xV(1)); | ||
|
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| SboxOUTxDO(0) <= SBoxT1xV(0) xor SBoxT1xV(4); | ||
| SboxOUTxDO(1) <= SBoxT1xV(1) xor SBoxT1xV(0); | ||
| SboxOUTxDO(2) <= not SBoxT1xV(2); | ||
| SboxOUTxDO(3) <= SBoxT1xV(3) xor SBoxT1xV(2); | ||
| SboxOUTxDO(4) <= SBoxT1xV(4); | ||
| end process sbox; | ||
|
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||
| end architecture structural; |
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