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Generate multiple iterations of the stress test code block as a loop #5
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Hi Gokul, This use case is not supported yet since we typically use endless wrappers and control the number of instructions executed/measure externally (e.g. killing the process or stopping the simulation after N cycles or instructions committed). Not sure what is your output format, if you are using a C and the compiling you can use the following wrappers:
You might need to double check register usage since the compilation process mess up things. If you are using another format wrapper (e.g. assembly or riscvtestp), then we need to implement that functionality. That can be done in two different ways:
Which format/wrapper are you using? Let me know, and I'll implement the necessary support. Thanks, |
Hi Ramon, Thanks for your response. An endless wrapper would work fine as well. I am using the RiscvTestsP wrapper and it would be great if it had the functionality. I have not tried the C format - maybe I can give that a shot too. Thinking ahead, I think it might be a useful feature if each loop iteration had some configurability. For example, if the memory addresses could be changed from one iteration to another (say, as some function of the iteration number), this might be useful in stressing the prefetcher. If you think this would be a useful usecase then maybe adding a pass to enable this might be a better option than directly doing so from the wrapper? Please let me know if I can provide any help from my end. Thanks! |
@rgokulsm, if you are using the Instead of creating the object like this:
do this:
Also there is a
Unfortunately, due to lack of documentation/examples all these details are hidden in the code. When time permits, we'll try to fix that, but in the meantime, feel free to ask anything. Regarding the memory pattern use case, I'll open a separate issue to discuss that. |
Thanks Ramon. I'm able to create an endless loop now. The code I use is: cwrapper = get_wrapper('RiscvTestsP') |
Hello,
I am generating micro-benchmarks for risc-v (based on risv_ipc) with the parameter --loop-size L which, in my understanding, sets the size of the building block (with SimpleBuildingBlockPass). After this the various passes act on this block.
I am interested in having the final generated code to loop over this instruction block multiple (i.e. a configurable N-times outer loop) times, so that the total instructions I would execute would be N*L i.e. so that I can have a longer stress test to run on the simulator.
Not sure if I can just add/edit a simple pass to enable this.
The current code I use:
passes = [
structure.SimpleBuildingBlockPass(self.args.loop_size),
initialization.InitializeRegistersPass(),
initialization.InitializeRegistersPass(v_value=(1.000000000000001, 64)),
instruction.SetInstructionTypeByProfilePass(thisdict),
address.UpdateInstructionAddressesPass(),
branch.BranchNextPass(),
register.DefaultRegisterAllocationPass(dd=GOK_REG_DIST),
address.UpdateInstructionAddressesPass()
]
for p in passes:
synth.add_pass(p)
Thanks,
Gokul
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