GitHub - JAnanthakrishnan/512-Bit-AES-Encryption: 512-bit AES using 128-bit AES in Verilog (FPGA-modelsim)

Hello world

Name		Name	Last commit message	Last commit date
Latest commit History 15 Commits
AES-512.pdf		AES-512.pdf
AES_decryption_512.v		AES_decryption_512.v
AES_encryption_512.v		AES_encryption_512.v
README.md		README.md
_config.yml		_config.yml
inv_key_gen.v		inv_key_gen.v
inv_mix_col.v		inv_mix_col.v
inv_sbox.v		inv_sbox.v
inv_shift_row.v		inv_shift_row.v
inv_sub_byte.v		inv_sub_byte.v
key_gen.v		key_gen.v
main_decryption.v		main_decryption.v
main_encryption128.v		main_encryption128.v
mix_col.v		mix_col.v
sbox.v		sbox.v
shift_row.v		shift_row.v
sub_byte.v		sub_byte.v
tb_aes_enc.v		tb_aes_enc.v
test.v		test.v

Provide feedback