Merge pull request #451 from JITx-Inc/dh/updates-from-old-demos

Pull fixes from old demos into dev.

components/analog-devices/ADM7154.stanza

@@ -64,5 +64,8 @@ public pcb-module module (v-out:Double) :
   net (ps.vout, vout)
   net (ps.gnd gnd)
 
+  schematic-group(self) = ADM7154
+  layout-group(self) = ADM7154
+
 public pcb-module module () : 
   inst i : module(1.2) 

components/marvell/88E1510-A0-NNB2C000.stanza

@@ -132,3 +132,7 @@ public pcb-module module :
   net (gnd xtal.gnd)
   net (xtal.p[2] phy.xtal-in)
   net (xtal.p[1], phy.xtal-out)
+
+  schematic-group(phy) = phy
+  schematic-group(self) = M88E1510-A0-NNB2C000
+  layout-group(self) = M88E1510-A0-NNB2C000

components/microsemi/A2F200M3F-FGG256I.stanza

@@ -309,13 +309,13 @@ public pcb-module module :
   for cap-count in [[47.0e-6, 1], [4.7e-6, 2]] do:
     val [capacitance, count]:[Double, Int] = cap-count
     for n in 0 to count do:
-      cap-strap(src-3V3.vdd, gnd, capacitance)
-      cap-strap(src-1V5.vdd, gnd, capacitance)
+      bypass-cap-strap(src-3V3.vdd, gnd, capacitance)
+      bypass-cap-strap(src-1V5.vdd, gnd, capacitance)
 
   for cap-count in [[47.0e-6 1] [4.7e-6 2] [0.47e-6 4]] do:
     val [capacitance, count]:[Double, Int] = cap-count
     for n in 0 to count do:
-      cap-strap(src-io.vdd, gnd, capacitance)
+      bypass-cap-strap(src-io.vdd, gnd, capacitance)
 
 
   net (sys-i2c[0].sda, fpga.I2C_0_SDA-GPIO[22])

components/nexperia/PUSB3FR4.stanza

@@ -0,0 +1,45 @@
+#use-added-syntax(jitx)
+defpackage ocdb/components/nexperia/PUSB3FR4 :
+  import core
+  import collections
+  import jitx
+  import jitx/commands
+  import ocdb/utils/box-symbol
+
+pcb-pad rect-smd-pad :
+  type = SMD
+  shape = Rectangle(0.250013, 0.68001)
+  layer(Paste(Top)) = Rectangle(0.250013, 0.68001)
+  layer(SolderMask(Top)) = Rectangle(0.250013, 0.68001)
+
+public pcb-landpattern C294620 :
+  pad p[1] : rect-smd-pad at loc(-1.0, -0.434989) on Top
+  pad p[2] : rect-smd-pad at loc(-0.499873, -0.434989) on Top
+  pad p[3] : rect-smd-pad at loc(0.0, -0.434989) on Top
+  pad p[4] : rect-smd-pad at loc(0.500127, -0.434989) on Top
+  pad p[5] : rect-smd-pad at loc(1.0, -0.434989) on Top
+  pad p[6] : rect-smd-pad at loc(1.0, 0.434963) on Top
+  pad p[7] : rect-smd-pad at loc(0.500127, 0.434963) on Top
+  pad p[8] : rect-smd-pad at loc(0.0, 0.434963) on Top
+  pad p[9] : rect-smd-pad at loc(-0.499873, 0.434963) on Top
+  pad p[10] : rect-smd-pad at loc(-1.0, 0.434963) on Top
+
+  layer(Silkscreen("F-SilkS", Top)) = Text(">REF", 1.0, C, loc(0.0, 2.016015), "", TrueTypeFont)
+  layer(Silkscreen("F-SilkS", Top)) = Polyline(0.15, [Arc(-1.016002, -1.397142, 0.0635000000000001, 0.0, 360.0)])
+
+public pcb-component component :
+  port CH : pin[[1 2 3 4]]
+  mpn = "PUSB3FR4"
+  manufacturer = "Nexperia"
+  pin-properties :
+    [pin:Ref | pads:Ref ... | side:Dir | electrical-type:String]
+    [CH[1] | p[1] p[10] | Left | "Unspecified"]
+    [CH[2] | p[2]  p[9] | Left | "Unspecified"]
+    [GND | p[3] p[8] | Left | "Unspecified"]
+    [CH[3] | p[4] p[7] | Left | "Unspecified"]
+    [CH[4] | p[5] p[6] | Left | "Unspecified"]
+
+  assign-landpattern(C294620)
+  make-box-symbol()
+
+  property(self.datasheet) = "https://datasheet.lcsc.com/lcsc/1810081417_Nexperia-PUSB3FR4_C294620.pdf"

components/nordic/nRF52840.stanza

@@ -3,7 +3,8 @@ defpackage ocdb/components/nordic/nRF52840 :
   import core
   import collections
   import math
-  import lang-utils
+  import lang-utils with:
+    prefix(min-max) => lang-
   import jitx
   import jitx/commands
 
@@ -202,61 +203,191 @@ public pcb-component component :
   make-box-symbol()
   assign-landpattern(xcvr-nrf52840-qiaa-r-pkg)
 
+  val driver = DigitalIO( CMOSOutput(min-max(0.0, 0.4), OffsetVoltage(-0.4, self.VDD[0])), 
+                          FractionalVoltage(0.3, self.VDD[0]), 
+                          FractionalVoltage(0.7, self.VDD[0]), self.VDD[0], self.VSS, 50.0e-9)
+
+  pcb-bundle io-pin : 
+    pin p
+
+  for p  in pins(self.P0) do :
+    supports io-pin :
+      io-pin.p => p
+    property(p.digital-io) = driver
+
+  for p  in pins(self.P1) do :
+    supports io-pin :
+      io-pin.p => p
+    property(p.digital-io) = driver
+
+  for i in 0 to 48 do :
+    supports gpio :
+      require io:io-pin 
+      gpio.gpio => io.p
+
+  for i in [02 03 04 05 28 29 30 31] do :
+    supports adc :
+      adc.adc => self.P0[i]
+
+  for i in 0 to 2 do :
+    supports i2c :
+      require pins:io-pin[2] 
+      i2c.sda => pins[0].p
+      i2c.scl => pins[1].p
+
+  for i in 0 to 3 do :
+    supports spi-controller() :
+      require pins:io-pin[4] 
+      spi-controller().copi => pins[0].p
+      spi-controller().cipo => pins[1].p
+      spi-controller().sck => pins[2].p
+      spi-controller().cs => pins[3].p
+
+  for i in 0 to 2 do :
+    supports uart([UART-RX UART-TX UART-CTS UART-RTS]) :
+      require pins:io-pin[4]
+      uart([UART-RX UART-TX UART-CTS UART-RTS]).tx => pins[0].p
+      uart([UART-RX UART-TX UART-CTS UART-RTS]).rx => pins[1].p
+      uart([UART-RX UART-TX UART-CTS UART-RTS]).rts => pins[2].p
+      uart([UART-RX UART-TX UART-CTS UART-RTS]).cts => pins[3].p
+
+  supports swd([SWD-SWO]) :
+    swd([SWD-SWO]).swdio => self.SWDIO
+    swd([SWD-SWO]).swdclk => self.SWDCLK
+    swd([SWD-SWO]).swo => self.P1[00]
+
+  supports reset :
+    reset.reset => self.P0[18]
+
   ; HFXO for 30ppm
-  property(XC2.crystal-oscillator) = CrystalOscillator(3.5e-3, 100.0e-6, 3.0e-12, 30.0e-6 * 32.0e6, 32.0e6)
+  property(self.XC2.crystal-oscillator) = CrystalOscillator(3.5e-3, 100.0e-6, 3.0e-12, 30.0e-6 * 32.0e6, 32.0e6)
   ; LFXO for 50ppm
-  property(P0[01].crystal-oscillator) = CrystalOscillator(3.1e-6, 0.5e-6, 4.0e-12, 50.0e-6 * 32.768e3, 32.768e3)
+  property(self.P0[01].crystal-oscillator) = CrystalOscillator(3.1e-6, 0.5e-6, 4.0e-12, 50.0e-6 * 32.768e3, 32.768e3)
 
-; This module is a WIP.
-public pcb-module module :
-  port usb : usb-2
+  supports low-freq-oscillator :
+    low-freq-oscillator.in => self.P0[0]
+    low-freq-oscillator.out => self.P0[1]
+
+doc: \<DOC>
+  NRF52840 reference module.
+  ## Args:
+  `include-lfo?:True|False = true` - include a 32.768kHz resonator in the design
+
+  `include-antenna?:True|False = true` - include an antenna and matching circuit in the design
+
+  `power-config:Int = 5` - circuit configuration from https://infocenter.nordicsemi.com/index.jsp?topic=%2Fps_nrf52840%2Fref_circuitry.html (currently supports 5, 6)
+
+  ## Example use:
+  ```
+    inst nrf : ocdb/components/nordic/nRF52840/module(include-lfo? = false, power-config = 6)
+  ```
+<DOC>
+public pcb-module module (-- include-LFO?:True|False = true, include-antenna?:True|False = true, power-config:Int = 5) :
   pin gnd
   inst mcu : ocdb/components/nordic/nRF52840/component
+  net (gnd, mcu.VSS, mcu.VSS_PA)
 
-  net (gnd, usb.vbus.gnd, mcu.VSS, mcu.VSS_PA)
-
-  ; Configure to be in normal voltage mode, DCDC1 enabled (config 5 from datasheet)
   ; Setup Bypass caps
-  for [pin_, cap_] in kvs([
-    mcu.DEC1    => 100.0e-9,
-    mcu.DEC3    => 100.0e-12,
-    mcu.DEC5    => 820.0e-12,
-    mcu.DECUSB  => 4.7e-6,
-    mcu.VBUS    => 4.7e-6,
-    mcu.DEC4    => 1.0e-6,
-    mcu.VDDH    => 4.7e-6,
-    mcu.VDD[0]  => 0.1e-6,
-    mcu.VDD[1]  => 0.1e-6,
-    mcu.VDD[2]  => 0.1e-6,
-    mcu.VDD[3]  => 1.0e-6,
-    mcu.VDD[4]  => 1.0e-6
-  ]) do:
-    bypass-cap-strap(pin_, gnd, cap_)
+  switch(power-config) :
+    5 : 
+      port usb : usb-2 ; USB enabled
+      pin vdd
+      net (gnd, usb.vbus.gnd)
+      net (mcu.VBUS, usb.vbus.vdd)
+      ; Configure to be in normal voltage mode, DCDC1 enabled (config 5 from datasheet)
+      for [pin_, cap_] in kvs([
+        mcu.DEC1    => 100.0e-9,
+        mcu.DEC3    => 100.0e-12,
+        mcu.DEC5    => 820.0e-12,
+        mcu.DECUSB  => 4.7e-6,
+        mcu.VBUS    => 4.7e-6,
+        mcu.DEC4    => 1.0e-6,
+        mcu.VDDH    => 4.7e-6,
+        mcu.VDD[0]  => 0.1e-6,
+        mcu.VDD[1]  => 0.1e-6,
+        mcu.VDD[2]  => 0.1e-6,
+        mcu.VDD[3]  => 1.0e-6,
+        mcu.VDD[4]  => 1.0e-6
+      ]) do:
+        val c = bypass-cap-strap(pin_, gnd, cap_)
+        schematic-group(c) = power
+        layout-group(c) = power
 
-  inst pwr-ind : smd-inductor([
-    "inductance" => 10.0e-6 
-    "min-current-rating" => 50.0e-3 ])
-
-  inst filt-ind : smd-inductor([
-    "inductance" => 15.0e-9, 
-    "min-self-resonant-frequency" => 2.0e9,
-    "material-core" => "ceramic"])
-
-  net (pwr-ind.p[1] mcu.DCCH)
-  net (pwr-ind.p[2] filt-ind.p[1])
-  net (mcu.DEC4 mcu.DEC6 filt-ind.p[2])
+      inst pwr-ind : smd-inductor([
+        "inductance" => 10.0e-6 
+        "min-current-rating" => 50.0e-3 ])
+
+      inst filt-ind : smd-inductor([
+        "inductance" => 15.0e-9, 
+        "min-self-resonant-frequency" => 2.0e9,
+        "material-core" => "ceramic"])
+
+      net (pwr-ind.p[1] mcu.DCCH)
+      net (pwr-ind.p[2] filt-ind.p[1])
+      net (mcu.DEC4 mcu.DEC6 filt-ind.p[2])
+
+      for i in 0 through 4 do : 
+        net (vdd mcu.VDDH mcu.VDD[i])
+    6 :
+      ; Battery power only, no USB, no NFC
+      pin vdd 
+
+      for [pin_, cap_] in kvs([
+        mcu.DEC1    => 100.0e-9,
+        mcu.DEC3    => 100.0e-12,
+        mcu.DEC5    => 820.0e-12,
+        mcu.DEC4    => 1.0e-6,
+        mcu.VDDH    => 4.7e-6,
+        mcu.VDD[0]  => 0.1e-6,
+        mcu.VDD[1]  => 0.1e-6,
+        mcu.VDD[2]  => 0.1e-6,
+        mcu.VDD[3]  => 1.0e-6,
+      ]) do:
+        val c = bypass-cap-strap(pin_, gnd, cap_)
+        schematic-group(c) = power
+        layout-group(c) = power
+      net (mcu.VBUS gnd)
+      net (mcu.DEC4 mcu.DEC6)
+      net (vdd mcu.VDDH)
+      no-connect(mcu.D+)
+      no-connect(mcu.D-)
+      for i in 0 through 4 do : 
+        net (vdd mcu.VDD[i])
+        ; Normal voltage mode.
+        property(mcu.VDD[i].power-pin) = PowerPin(min-typ-max(1.7, 3.0, 3.6))
+      property(mcu.VDDH.power-pin) = PowerPin(min-typ-max(1.7, 3.0, 3.6))
 
-  for i in 0 through 4 do : 
-    net (mcu.VDD[0] mcu.VDD[i])
+    else :
+      false
 
-  inst lfosc : ocdb/components/epson/FC-135/component
-  net (mcu.P0[0] lfosc.p[1])
-  net (mcu.P0[1] lfosc.p[2])
-  val lf-cb = add-xtal-caps(lfosc, gnd)
-  check-resonator(lfosc, property(mcu.P0[1].crystal-oscillator), lf-cb)
+  if include-LFO? :  
+    inst lfosc : ocdb/components/epson/FC-135/component
+    require lfo : low-freq-oscillator from mcu
+    net (lfo.in lfosc.p[1])
+    net (lfo.out lfosc.p[2])
+    val lf-cb = add-xtal-caps(lfosc, gnd)
+    check-resonator(lfosc, property(mcu.P0[1].crystal-oscillator), lf-cb)
 
   inst hfosc : ocdb/components/epson/TSX-3225/component(32.0e6)
   net (mcu.XC1 hfosc.p[1])
   net (mcu.XC2 hfosc.p[2])
   val hf-cb = add-xtal-caps(hfosc, gnd)
   check-resonator(hfosc, property(mcu.XC2.crystal-oscillator), hf-cb)
+
+  ; Antenna
+  if include-antenna? :
+    inst ant : inverted-f-antenna-cmp
+    inst c3 : ceramic-cap(["capacitance" => 0.8e-12 "temperature-coefficient.code" => "C0G" "case" => "0402"])
+    inst c4 : ceramic-cap(["capacitance" => 0.5e-12 "temperature-coefficient.code" => "C0G" "case" => "0402"])
+    inst l2 : smd-inductor(["inductance" => 4.7e-9 "min-self-resonant-frequency" => 7.0e6 "min-quality-factor" => 8.0 "case" => "0402"])
+    net (gnd c3.p[2] c4.p[2] ant.gnd)
+    net (mcu.ANT c3.p[1] l2.p[1])
+    net launch (l2.p[2] c4.p[1] ant.launch)
+    ; 50 ohm line on a 1.5mm h CBCPW
+    property(launch.net-class) = NetClass(`ANT, [`min-trace => 0.5 `min-space => 0.2])
+    schematic-group([ant c3 c4 l2]) = util
+
+  schematic-group(mcu, 2) = util
+  schematic-group(mcu, 3) = power
+  schematic-group(self) = NRF52840
+  layout-group(self) = NRF52840

components/pulse-electronics/J0G-0009NL.stanza

@@ -65,9 +65,8 @@ pcb-landpattern pulse-J0G-0009NL-pkg :
   pad p[18] : pth-pad(1.57 / 2.0) at loc(17.58 / 2.0, 0.0)  
   pad p[19] : pth-pad(1.57 / 2.0) at loc(-17.58 / 2.0, 0.0)
 
-  layer(Cutout()) = Union([ 
-    Circle(9.65 / 2.0, 0.0, 1.6)
-    Circle(-9.65 / 2.0, 0.0, 1.6)])
+  layer(Cutout()) = Circle(9.65 / 2.0, 0.0, 1.6)
+  layer(Cutout()) =   Circle(-9.65 / 2.0, 0.0, 1.6)
   layer(Courtyard(Top)) = Rectangle(17.58, 24.13, loc(0.0, 1.5))
 
 public pcb-module module :

components/te-connectivity/2102735-1.stanza

@@ -30,6 +30,7 @@ public pcb-component component:
 
   make-box-symbol()
   assign-landpattern(te-2102735-1-pkg)
+  property(self.rated-temperature) = min-max(-55.0, 105.0)
 
 pcb-landpattern te-2102735-1-pkg :
 

components/te-connectivity/2102736-1.stanza

@@ -29,6 +29,7 @@ public pcb-component component :
   reference-prefix = "P"
   make-box-symbol()
   assign-landpattern(te-2102736-1-pkg)
+  property(self.rated-temperature) = min-max(-55.0, 105.0)
 
 pcb-landpattern te-2102736-1-pkg :
 

components/texas-instruments/TLV62130.stanza

@@ -102,7 +102,8 @@ public pcb-module module (v-out:Double) :
   cap-strap(vout, gnd, 22.0e-6)
 
   property(l.p[2].power-supply-pin) = PowerSupplyPin(typ(v-out), 3.0) 
-
+  schematic-group(self) = TLV62130RGTR
+  layout-group(self) = TLV62130RGTR