- 🌱 I’m currently learning Verilog and FPGA development.
- 🔭 I’ve explored RISC-V, Django, Flutter etc
- Connect with me on LinkedIn
Student at College of engineering, Trivandrum.
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College of engineering, Trivandrum
- Kozhikode
- @Javeed1Ahd
- in/javeed-ahmad
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apb_adv_timer
apb_adv_timer PublicForked from pulp-platform/apb_adv_timer
Advanced timer with APB interface
SystemVerilog 1
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