Projects for the ULX3S. There are two folders
- icestudio: projects using Icestudio: https://icestudio.io/
- apio: projects in verilog using Apio: https://apiodoc.readthedocs.io
Same as Apio project but in Icestudio. Color from camera needs some improvement. Color filter with a 50MHz clock
Capture 320x240 image from ov7670
btn2 switches between RGB (RN), YUV (YN), and color test bar for both (RT and YT).
btn6 (right) switches between color filters. If color filter active, there will be a smal square with the active color filter (after RN, YN, RT, YT). The color filter will not have effect in YUV mode because the only the Y is taken, so there is no color in the image.
btn1 is reset
To programm the FPGA fujprog is used after generating the .bit file with Icestudio. https://github.com/kost/fujprog
Video: https://youtu.be/PyhVvvYumsc
See the Alhambra II project to see the block diagram.
Capture 320x240 image from ov7670, btn2 switches between RGB, YUV, and color test bar for both.
btn1 is reset. It should be reset for a second, then wait around 30 seconds until led[6] is ON
Same as previous but using a 50MHz clock, since there were timming warnings at 100MHz Capture 320x240 image from ov7670, btn2 switches between RGB, YUV, and color test bar for both.
btn1 is reset
Same as Icestudio project. Color processing with a 50MHz clock Capture 320x240 image from ov7670, btn2 switches between RGB, YUV, and color test bar for both.
btn1 is reset. It should be reset for a second, then wait around 30 seconds until led[6] is ON
btn2 switches between RGB (RN), YUV (YN), and color test bar for both (RT and YT).
btn6 (right) switches between color filters. If color filter active, there will be a smal square with the active color filter (after RN, YN, RT, YT). The color filter will not have effect in YUV mode because the only the Y is taken, so there is no color in the image.
Same as ov7670_rgb_yuv_320x240_colorfilter but usign the camera PMOD
Port GP17-OV7670_PWDN didn't work when camera powerdown was assigned deep in the hierarchy, but when assigned in the top module it worked
Two cameras and VGA. 50MHz clock. Same as Xilinx Nexys4DDR project. Each camera image is 160x120. Color processing independently on each camera. Proximity and centroid.
Block diagram
Pin connection:
Three cameras and VGA. 50MHz clock. Each camera image is 160x120. Color processing independently on each camera. Proximity and centroid.
Three cameras and VGA. 50MHz clock. Each camera image is 160x120. Color processing independently on each camera. Proximity and centroid.
- FPGA clock is 50MHz
- xclk (ov7670_clk) generated by the FPGA to camera is clk50mhz/4 -> 12.5 MHz - 80 ns. Camera clock should be
- min: 10 MHz -- typ: 24 MHz -- Max: 48 MHz
- Period : max: 100 ns -- typ: 42 ns -- Max: 21 ns
- pclk is the clock from the camera. These are some camera registers involved:
- 0x11: CLKRC: Internal Clock
- [7]=1: Reserved **Implementation Guide says 0, but 1 seems stable (some times 0 others 1)
- [6]=0: Use pre-scale
- [5:0]: Interal clock pre-scalar. F(internal clk) = F(input clk)/([5:0]+1)
- [5:0]= 0: No prescale (internal clk)
- 0x3E: COM14 Common Control 14 = 0x1A
- [4]=1: Scaling PCLK and DCW enabled. Controlled by [2:0] and SCALING_PCLK_DIV
- [3]=1: Manual scaling enabled for predefined modes such QVGA
- [2:0] PCLK divided when COM14[4]=1
- [2:0]=010: Divided by 4-> QQVGA: 160x12
- 0x11: CLKRC: Internal Clock
The resulting frames per seconds should be around 15 fps (~67ms). Not sure because I don't get the same calculation as the datasheet.
The FPGA process 160x120 pixels, at 20ns (50MHz) 384us, so more than 100 times faster than the camera.
Left and center cameras are for the robot to follow an object. The right camera is to follow another object with a turret guided by a servo.
The commands are given to the GoPiGo3 board:
- The robot is commanded by two (right & left motor) 16-bit DPS (degrees per second) signals
- The servo is commanded by a 10-bit signed signal. 0: 0 degrees; -500: -90 degrees; 500: 90 degrees
Other signals:
newframe: this signal is generated in the ov7670 camera capture. Indicates when a complete frame has been received. This signal is just a clock cycle. After this signal is received, there are at least 30 camera lines. Each line is at least 784 x 2 ov7670_clk (pclk). Multiplied x2 because it takes 2 camera clk cycles to send a pixel Having pclk is 80ns (12.5 MHz), it would be around 125 us before the first pixel is received. So it will be around 6272 FPGA clock cycles (20ns-50MHz). With these times, the FPGA would be in the 39th line when the first pixel is received, and since the FPGA process the image faster than the pixels are received, the old frame will be processed before the new frame fills the buffer
Blocks for 2 camera guiding robot:
Blocks for 1 camera on turret:
Projects for the Alhambra II FPGA. There are two folders:
- icestudio: projects using Icestudio: https://icestudio.io/
- apio: projects in verilog using Apio: https://apiodoc.readthedocs.io
Same project as the Apio ov7670_rgb444_80x60 adapted for icestudio.
Same project as the Apio ov7670_rgb_yuv_80x60 adapted for icestudio.
SW1: reset, necessary to start
SW2 choose between:
RGB -> RGB test -> YUV -> YUV test -> RGB
The drawback of choosing is that you loose pins for YUV, and you can only get 3 bits of gray color, without choosing you could get 5
The block diagram is the following, which is the same for the Apio project, and also for the ULX3S examples
Same project as the Apio ov7670_yuv_80x60_sobel_50mhz adapted for icestudio.
Shows image in grayscale
Once it is loaded, press SW1 to reset the camera
Press SW2 to change to Sobel Horizontal Filter -> Sobel Vertical Filter -> No filter (in gray scale)
Same as the Apio ov7670_rgb444_80x60_color_centroid project
This project is included with motor control in the Icestudio FPGA-Robotics Collection: ../blocks/icestudio/icestudioCollection/FPGA-Robotics-v1-stable
It is important to connect the camera with short wires (10 cm at most)
Display a test card on a 640x480 VGA with Alhambra II using 100MHz PLL generated clock
Display 80x60 video on a VGA from the ov7670 camera using Alhambra II
Camera in test mode
ov7670 camera capture, color processing and 80x60 VGA display using Alhambra II
Camera in test mode QQVGA/2 (80x60)
50 MHz clock ov7670 camera capture, color processing, 80x60 VGA display using Alhambra II, and shows on the leds where the horizontal centroid is
sw2 selects the color for the filter, initially there is no filter, so press it once to have red filter, and then: green -> blue -> yellow -> magenta -> cyan -> white -> none -> red -> ...
The VGA shows where the horizontal centroid is and also the proximity of the object (counts how many pixels are detected), the result is reduced to 8 bits. Maximum value is when half of the pixels are detected. Then 1/3, 1/6, 1/12, 1/24, 1/48, 1/96, and less.
The simplified diagram is the following:
SW1: reset, necessary to start
SW2 choose between:
RGB -> RGB test -> YUV -> YUV test -> RGB
The drawback of choosing is that you lose pins for YUV, and you can only get 3 bits of gray color, without choosing you could get 5
The same as the previous, but configures the PLL to have a clock of 50MHz instead of 100MHz to see if there is any improvement. It doesn't seem to be; however, the timming analysis suggest a clock frequency of 80MHz (or less)
SW1: reset, necessary to start
SW2 choose between: No filter grayscale -> Sobel horizontal filter -> Sobel Vertical filter -> No filter grayscale.
When pressed more than a second -> test mode
Same as previous, but configures the PLL to have a clock of 50MHz instead of 100MHz to see if there is any improvement. It doesn't seem to be; however, the timing analysis suggest a clock frequency of 80MHz (or less).
Interfacing the OV7670 camera with a Xilinx Nexys4 FPGA and displaying the video through VGA. There are VHDL and Verilog versions
Option to choose between RGB or YUV (only Y). Also camera can be in test mode or normal capture
Option to choose between RGB or YUV (only Y). Also, camera can be in test mode or normal capture. And choose color filter when in RGB and edge Sobel filter when in YUV
Same as ULX3S project but for Xilinx Nexys4DDR. Only in verilog
Same as AlhambraII project but for Xilinx Nexys4DDR. Only in verilog. Using the same 50MHz clock
Color centroid and proximity calculation using 160x120 image
Two cameras, color centroid and proximity calculation using 160x120 image
There are 2 .ucf files, using the radiona PMOD for the OV7670 cameras or using cables.
