This template project contains an HDL Centipede core, with a supporting verilator-based C++ simulation front-end.
The simulation currently supports the following features in order to make developing cores for MiSTer easier:
- Controllable sim speed with continuous, single and multi-step options
- VGA output is captured and displayed with optional zoom and rotation
- ROM upload (simulating the ioctl elements of HPS)
- Input mappings
- Verilog
$displayoutput is redirected to the UI debug console
- Install WSL2 with Ubuntu
- Install Visual Studio 2022 (Community edition is fine) with the C++ workload
This project has been built with Verilator v4.204. Any change to the verilator version will require changes to allow the project to build, so it is advised to stick with 4.204. To install this version, run the following commands from a temporary directory:
# Prerequisites:
sudo apt-get install git perl python3 make autoconf g++ flex bison ccache
sudo apt-get install libgoogle-perftools-dev numactl perl-doc
sudo apt-get install zlibc zlib1g zlib1g-dev
git clone https://github.com/verilator/verilator
unset VERILATOR_ROOT
cd verilator
git pull
git checkout v4.204
autoconf
./configure
make -j `nproc`
sudo make install
The /verilator directory contains all simulation-related resources. Some important resources are:
/verilator/centipede_sim.v- Surrogate top module to host the HDL code/verilator/verilate.sh- Bash script which runs verilator against the HDL files in/rtl/verilator/obj_dir/- Contains the C++ source generated by verilator/verilator/sim/- Contains the C++ source files to host the simulation/verilator/sim/imgui- Contains the Dear Imgui C++ includes/verilator/sim/vinc- Contains the Verilator C++ includes
Run verilate.sh after changes to any HDL code. Visual Studio will then automatically re-build on the next run.
IMPORTANT: Run the simulation project in Release mode or your framerate will be very disappointing!