JitArm64: Implement indexed paired loadstore instructions

After writing 23b81ef without realizing that we hadn't actually implemented the indexed paired loadstore instructions yet, I am now implementing them.
JosJuice · Aug 17, 2021 · b24b79e · b24b79e
1 parent d162015
commit b24b79e
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Showing 3 changed files with 33 additions and 26 deletions.
diff --git a/Source/Core/Core/PowerPC/JitArm64/Jit.h b/Source/Core/Core/PowerPC/JitArm64/Jit.h
@@ -159,8 +159,8 @@ class JitArm64 : public JitBase, public Arm64Gen::ARM64CodeBlock, public CommonA
   void ps_cmpXX(UGeckoInstruction inst);
 
   // Loadstore paired
-  void psq_l(UGeckoInstruction inst);
-  void psq_st(UGeckoInstruction inst);
+  void psq_lXX(UGeckoInstruction inst);
+  void psq_stXX(UGeckoInstruction inst);
 
   void ConvertDoubleToSingleLower(size_t guest_reg, Arm64Gen::ARM64Reg dest_reg,
                                   Arm64Gen::ARM64Reg src_reg);

diff --git a/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStorePaired.cpp b/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStorePaired.cpp
@@ -15,7 +15,7 @@
 
 using namespace Arm64Gen;
 
-void JitArm64::psq_l(UGeckoInstruction inst)
+void JitArm64::psq_lXX(UGeckoInstruction inst)
 {
   INSTRUCTION_START
   JITDISABLE(bJITLoadStorePairedOff);
@@ -39,28 +39,32 @@ void JitArm64::psq_l(UGeckoInstruction inst)
   gpr.Lock(ARM64Reg::W0, ARM64Reg::W1, ARM64Reg::W2, ARM64Reg::W30);
   fpr.Lock(ARM64Reg::Q0, ARM64Reg::Q1);
 
-  const ARM64Reg arm_addr = gpr.R(inst.RA);
   constexpr ARM64Reg scale_reg = ARM64Reg::W0;
   constexpr ARM64Reg addr_reg = ARM64Reg::W1;
   constexpr ARM64Reg type_reg = ARM64Reg::W2;
   ARM64Reg VS;
 
   if (inst.RA || update)  // Always uses the register on update
   {
-    if (offset >= 0)
-      ADD(addr_reg, arm_addr, offset);
+    if (indexed)
+      ADD(addr_reg, gpr.R(inst.RA), gpr.R(inst.RB));
+    else if (offset >= 0)
+      ADD(addr_reg, gpr.R(inst.RA), offset);
     else
-      SUB(addr_reg, arm_addr, std::abs(offset));
+      SUB(addr_reg, gpr.R(inst.RA), std::abs(offset));
   }
   else
   {
-    MOVI2R(addr_reg, (u32)offset);
+    if (indexed)
+      MOV(addr_reg, gpr.R(inst.RB));
+    else
+      MOVI2R(addr_reg, (u32)offset);
   }
 
   if (update)
   {
-    gpr.BindToRegister(inst.RA, true);
-    MOV(arm_addr, addr_reg);
+    gpr.BindToRegister(inst.RA, false);
+    MOV(gpr.R(inst.RA), addr_reg);
   }
 
   if (js.assumeNoPairedQuantize)
@@ -101,7 +105,7 @@ void JitArm64::psq_l(UGeckoInstruction inst)
   fpr.Unlock(ARM64Reg::Q0, ARM64Reg::Q1);
 }
 
-void JitArm64::psq_st(UGeckoInstruction inst)
+void JitArm64::psq_stXX(UGeckoInstruction inst)
 {
   INSTRUCTION_START
   JITDISABLE(bJITLoadStorePairedOff);
@@ -158,8 +162,6 @@ void JitArm64::psq_st(UGeckoInstruction inst)
 
   gpr.Lock(ARM64Reg::W0, ARM64Reg::W1, ARM64Reg::W2, ARM64Reg::W30);
 
-  const ARM64Reg arm_addr = gpr.R(inst.RA);
-
   constexpr ARM64Reg scale_reg = ARM64Reg::W0;
   constexpr ARM64Reg addr_reg = ARM64Reg::W1;
   constexpr ARM64Reg type_reg = ARM64Reg::W2;
@@ -173,20 +175,25 @@ void JitArm64::psq_st(UGeckoInstruction inst)
 
   if (inst.RA || update)  // Always uses the register on update
   {
-    if (offset >= 0)
+    if (indexed)
+      ADD(addr_reg, gpr.R(inst.RA), gpr.R(inst.RB));
+    else if (offset >= 0)
       ADD(addr_reg, gpr.R(inst.RA), offset);
     else
       SUB(addr_reg, gpr.R(inst.RA), std::abs(offset));
   }
   else
   {
-    MOVI2R(addr_reg, (u32)offset);
+    if (indexed)
+      MOV(addr_reg, gpr.R(inst.RB));
+    else
+      MOVI2R(addr_reg, (u32)offset);
   }
 
   if (update)
   {
-    gpr.BindToRegister(inst.RA, true);
-    MOV(arm_addr, addr_reg);
+    gpr.BindToRegister(inst.RA, false);
+    MOV(gpr.R(inst.RA), addr_reg);
   }
 
   if (js.assumeNoPairedQuantize)

diff --git a/Source/Core/Core/PowerPC/JitArm64/JitArm64_Tables.cpp b/Source/Core/Core/PowerPC/JitArm64/JitArm64_Tables.cpp
@@ -78,12 +78,12 @@ constexpr std::array<GekkoOPTemplate, 54> primarytable{{
     {54, &JitArm64::stfXX},  // stfd
     {55, &JitArm64::stfXX},  // stfdu
 
-    {56, &JitArm64::psq_l},   // psq_l
-    {57, &JitArm64::psq_l},   // psq_lu
-    {60, &JitArm64::psq_st},  // psq_st
-    {61, &JitArm64::psq_st},  // psq_stu
+    {56, &JitArm64::psq_lXX},   // psq_l
+    {57, &JitArm64::psq_lXX},   // psq_lu
+    {60, &JitArm64::psq_stXX},  // psq_st
+    {61, &JitArm64::psq_stXX},  // psq_stu
 
-    // missing: 0, 1, 2, 5, 6, 9, 22, 30, 62, 58
+    // missing: 0, 1, 2, 5, 6, 9, 22, 30, 58, 62
 }};
 
 constexpr std::array<GekkoOPTemplate, 13> table4{{
@@ -125,10 +125,10 @@ constexpr std::array<GekkoOPTemplate, 17> table4_2{{
 }};
 
 constexpr std::array<GekkoOPTemplate, 4> table4_3{{
-    {6, &JitArm64::FallBackToInterpreter},   // psq_lx
-    {7, &JitArm64::FallBackToInterpreter},   // psq_stx
-    {38, &JitArm64::FallBackToInterpreter},  // psq_lux
-    {39, &JitArm64::FallBackToInterpreter},  // psq_stux
+    {6, &JitArm64::psq_lXX},    // psq_lx
+    {7, &JitArm64::psq_stXX},   // psq_stx
+    {38, &JitArm64::psq_lXX},   // psq_lux
+    {39, &JitArm64::psq_stXX},  // psq_stux
 }};
 
 constexpr std::array<GekkoOPTemplate, 13> table19{{