Fixes for DSTUA TST165, TST172, and TST173

KS10FPGA · Jan 8, 2022 · 129db73 · 129db73
1 parent 0f484e0
commit 129db73
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Showing 4 changed files with 32 additions and 12 deletions.
diff --git a/fpga/ks10/mt/mt.sv b/fpga/ks10/mt/mt.sv
@@ -141,7 +141,7 @@ module MT (
    // Only the MTMR and the MTAS registers can be written during an operation.
    //
 
-   logic         mtDRY;                                 // MTDS[DRY]
+   logic         mtDRY;
 
    wire          mtWRCS1  =   mtWRITE & mtSEL & (mtREGSEL == mtREGCS1) &  mtDRY;
    wire          mtWRFC   =   mtWRITE & mtSEL & (mtREGSEL == mtREGFC ) &  mtDRY;
@@ -382,7 +382,7 @@ module MT (
    wire mtSETOPI  = 0;                  // Operation Incomplete  (MTER[OPI]) : FIXME: Not implemented
    wire mtSETDTE  = 0;                  // Drive Timing Error    (MTER[DTE]) : FIXME: Not implemented
    wire mtSETFCE  = 0;                  // Frame Count Error     (MTER[FCE]) : FIXME: Not implemented
-   wire mtSETDPAR = 0;                  // Data Bus Parity Error (MTER[DPAR]): FIXME: Not implemented
+   wire mtSETDPAR = 0;                  // Data Bus Parity Error (MTER[DPAR]): Not testable with RH11.  See DSTUA TST67.
 
    //
    // MT Frame Count Register (MTFC)
@@ -529,11 +529,20 @@ module MT (
    );
 
    //
-   // RH11 Parity Test of receive data
-   //  Invert parity in Maintenance mode and with Even Parity OP
+   // Controller Parity Error
+   //  Asserted when accessing a register with even parity
+   //  Sets RHCS1[CPE]
    //
 
-   assign massbus.mbINVPAR = `mtMR_MM(mtMR) & (`mtMR_MOP(mtMR) == `mtMROP_EVPAR);
+   assign massbus.mbCPE = `mtMR_MM(mtMR) & (`mtMR_MOP(mtMR) == `mtMROP_EVPAR);
+
+   //
+   // Data Parity Error
+   //  Asserted when performing an NPR operation with even parity.
+   //  Sets RHCS2[DPE]
+   //
+
+   assign massbus.mbDPE = `mtMR_MM(mtMR) & (`mtMR_MOP(mtMR) == `mtMROP_EVPAR) & massbus.mbREQO;
 
    //
    // Multiplex registers back to RH11

diff --git a/fpga/ks10/rh11/rh11.sv b/fpga/ks10/rh11/rh11.sv
@@ -24,7 +24,7 @@
 //
 ////////////////////////////////////////////////////////////////////////////////
 //
-// Copyright (C) 2012-2021 Rob Doyle
+// Copyright (C) 2012-2022 Rob Doyle
 //
 // This source file may be used and distributed without restriction provided
 // that this copyright statement is not removed from the file and that any
@@ -397,7 +397,7 @@ module RH11 (
    //  Massbus device is sending inverted parity to RH11 in maintenance mode.
    //
 
-   wire rhSETCPE = rhREAD & massbus.mbINVPAR;
+   wire rhSETCPE = rhREAD & massbus.mbCPE;
 
    //
    // RH11 Control/Status #1 (RHCS1) Register
@@ -490,6 +490,7 @@ module RH11 (
       .rhSETDLT   (rhSETDLT),
       .rhSETNED   (rhSETNED),
       .rhSETNEM   (rhSETNEM),
+      .rhSETDPE   (massbus.mbDPE),
       .rhSETWCE   (massbus.mbWCE),
       .rhBUFIR    (rhBUFIR),
       .rhBUFOR    (rhBUFOR),

diff --git a/fpga/ks10/rh11/rhcs2.v b/fpga/ks10/rh11/rhcs2.v
@@ -13,7 +13,7 @@
 //
 ////////////////////////////////////////////////////////////////////////////////
 //
-// Copyright (C) 2012-2021 Rob Doyle
+// Copyright (C) 2012-2022 Rob Doyle
 //
 // This source file may be used and distributed without restriction provided
 // that this copyright statement is not removed from the file and that any
@@ -58,6 +58,7 @@ module RHCS2 (
       input  wire         rhSETWCE,             // Set WCE
       input  wire         rhSETNED,             // Set NED
       input  wire         rhSETNEM,             // Set NEM
+      input  wire         rhSETDPE,             // Set DPE
       input  wire         rhBUFIR,              // Status IR
       input  wire         rhBUFOR,              // Status OR
       output wire [15: 0] rhCS2                 // CS2 Output
@@ -223,7 +224,15 @@ module RHCS2 (
    //  M7297/PACA/E10 (SYNC PE)
    //
 
-   wire rhcs2DPE = 0;
+   reg rhcs2DPE;
+
+   always @(posedge clk)
+     begin
+        if (rst | devRESET | rhCLR)
+          rhcs2DPE <= 0;
+        else if (rhSETDPE)
+          rhcs2DPE <= 1;
+     end
 
    //
    // RHCS2 Output Ready

diff --git a/fpga/ks10/rpxx/rp.sv b/fpga/ks10/rpxx/rp.sv
@@ -24,7 +24,7 @@
 //
 ////////////////////////////////////////////////////////////////////////////////
 //
-// Copyright (C) 2012-2021 Rob Doyle
+// Copyright (C) 2012-2022 Rob Doyle
 //
 // This source file may be used and distributed without restriction provided
 // that this copyright statement is not removed from the file and that any
@@ -265,10 +265,11 @@ module RP (
    assign massbus.mbDVA    = 1;
 
    //
-   // Parity Test from RP
+   // Parity Tests from RP
    //
 
-   assign massbus.mbINVPAR = 0;
+   assign massbus.mbCPE = 0;
+   assign massbus.mbDPE = 0;
 
    //
    // ACLO