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Documentation/devicetree/bindings/display/msm/adreno-3xx.yaml
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause | ||
%YAML 1.2 | ||
--- | ||
$id: http://devicetree.org/schemas/display/msm/qcom,adreno-3xx.yaml# | ||
$schema: http://devicetree.org/meta-schemas/core.yaml# | ||
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title: Qualcomm Adreno 3xx GPU | ||
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maintainers: | ||
- Rob Clark <robdclark@gmail.com> | ||
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description: | ||
Device tree bindings for Adreno 300 series of GPU. | ||
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$ref: /schemas/display/msm/adreno-common.yaml# | ||
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allOf: | ||
- if: | ||
properties: | ||
compatible: | ||
contains: | ||
enum: | ||
- qcom,adreno-306.0 | ||
then: | ||
properties: | ||
clocks: | ||
minItems: 6 | ||
maxItems: 6 | ||
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clock-names: | ||
items: | ||
- const: core | ||
description: GPU Core clock | ||
- const: iface | ||
description: GPU Interface clock | ||
- const: mem | ||
description: GPU Memory clock | ||
- const: mem_iface | ||
description: GPU Memory Interface clock | ||
- const: alt_mem_iface | ||
description: GPU Memory Interface clock | ||
- const: gfx3d | ||
description: GPU RBBM Timer for Adreno 5xx series | ||
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reg-names: | ||
items: | ||
- const: kgsl_3d0_reg_memory | ||
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required: | ||
- clocks | ||
- clock-names | ||
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- if: | ||
properties: | ||
compatible: | ||
contains: | ||
enum: | ||
- qcom,adreno-305.18 | ||
- qcom,adreno-330.1 | ||
then: | ||
properties: | ||
clocks: | ||
minItems: 3 | ||
maxItems: 3 | ||
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clock-names: | ||
items: | ||
- const: core | ||
description: GPU Core clock | ||
- const: iface | ||
description: GPU Interface clock | ||
- const: mem_iface | ||
description: GPU Memory Interface clock | ||
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reg-names: | ||
items: | ||
- const: kgsl_3d0_reg_memory | ||
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required: | ||
- clocks | ||
- clock-names | ||
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examples: | ||
- | | ||
// Example a3xx/4xx: | ||
#include <dt-bindings/clock/qcom,mmcc-msm8974.h> | ||
#include <dt-bindings/clock/qcom,rpmcc.h> | ||
#include <dt-bindings/interrupt-controller/irq.h> | ||
#include <dt-bindings/interrupt-controller/arm-gic.h> | ||
gpu: gpu@fdb00000 { | ||
compatible = "qcom,adreno-330.2", "qcom,adreno"; | ||
reg = <0xfdb00000 0x10000>; | ||
reg-names = "kgsl_3d0_reg_memory"; | ||
clock-names = "core", "iface", "mem_iface"; | ||
clocks = <&mmcc OXILI_GFX3D_CLK>, | ||
<&mmcc OXILICX_AHB_CLK>, | ||
<&mmcc OXILICX_AXI_CLK>; | ||
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; | ||
interrupt-names = "kgsl_3d0_irq"; | ||
sram = <&gpu_sram>; | ||
power-domains = <&mmcc OXILICX_GDSC>; | ||
operating-points-v2 = <&gpu_opp_table>; | ||
iommus = <&gpu_iommu 0>; | ||
#cooling-cells = <2>; | ||
}; | ||
ocmem@fdd00000 { | ||
compatible = "qcom,msm8974-ocmem"; | ||
reg = <0xfdd00000 0x2000>, | ||
<0xfec00000 0x180000>; | ||
reg-names = "ctrl", "mem"; | ||
clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, | ||
<&mmcc OCMEMCX_OCMEMNOC_CLK>; | ||
clock-names = "core", "iface"; | ||
#address-cells = <1>; | ||
#size-cells = <1>; | ||
ranges = <0 0xfec00000 0x100000>; | ||
gpu_sram: gpu-sram@0 { | ||
reg = <0x0 0x100000>; | ||
}; | ||
}; |
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