Add support for RSP vector control register names (ctc2/cfc2)

Kingcom · May 23, 2018 · 0450d1a · 0450d1a
1 parent 5996abc
commit 0450d1a
Show file tree

Hide file tree

Showing 4 changed files with 21 additions and 2 deletions.
diff --git a/Archs/MIPS/CMipsInstruction.h b/Archs/MIPS/CMipsInstruction.h
@@ -15,6 +15,7 @@ enum class MipsRegisterType
 	VfpuMatrix,
 	RspCop0,
 	RspVector,
+	RspVectorControl,
 	RspBroadcastElement,
 	RspScalarElement,
 	RspOffsetElement

diff --git a/Archs/MIPS/MipsOpcodes.cpp b/Archs/MIPS/MipsOpcodes.cpp
@@ -557,9 +557,9 @@ const tMipsOpcode MipsOpcodes[] = {
 //  hi |-------|-------|-------|-------|-------|-------|-------|-------|
 
 	{ "mfc2",	"t,RsRo",		MIPS_COP2(0x00),			MA_RSP, 0 },
-	{ "cfc2",	"t,d",			MIPS_COP2(0x02),			MA_RSP, 0 },
+	{ "cfc2",	"t,Rc",			MIPS_COP2(0x02),			MA_RSP, 0 },
 	{ "mtc2",	"t,RsRo",		MIPS_COP2(0x04),			MA_RSP, 0 },
-	{ "ctc2",	"t,d",			MIPS_COP2(0x06),			MA_RSP, 0 },
+	{ "ctc2",	"t,Rc",			MIPS_COP2(0x06),			MA_RSP, 0 },
 	// VVVVVV VVVVV ttttt -------- C DDDDDDD
 	{ "mfv",	"t,vd",			MIPS_COP2(0x03),			MA_PSP,	MO_VFPU|MO_VFPU_SINGLE },
 	{ "mfvc",	"t,vc",			MIPS_COP2(0x03) | 0x80,		MA_PSP,	MO_VFPU },

diff --git a/Archs/MIPS/MipsParser.cpp b/Archs/MIPS/MipsParser.cpp
@@ -85,6 +85,10 @@ const MipsRegisterDescriptor mipsRspCop0Registers[] = {
 	{ L"dpc_tmem", 15 },
 };
 
+const MipsRegisterDescriptor mipsRspVectorControlRegisters[] = {
+	{ L"vco", 0 },		{ L"vcc", 1 }, 		{ L"vce", 2 },
+};
+
 const MipsRegisterDescriptor mipsRspVectorRegisters[] = {
 	{ L"v0", 0 },		{ L"v1", 1 },		{ L"v2", 2 },		{ L"v3", 3 },
 	{ L"v4", 4 },		{ L"v5", 5 },		{ L"v6", 6 },		{ L"v7", 7 },
@@ -279,6 +283,16 @@ bool MipsParser::parseRspCop0Register(Parser& parser, MipsRegisterValue& dest)
 	return parseRegisterTable(parser,dest,mipsRspCop0Registers,ARRAY_SIZE(mipsRspCop0Registers));
 }
 
+bool MipsParser::parseRspVectorControlRegister(Parser& parser, MipsRegisterValue& dest)
+{
+	dest.type = MipsRegisterType::RspVectorControl;
+
+	if (parseRegisterNumber(parser, dest, 32))
+		return true;
+
+	return parseRegisterTable(parser,dest,mipsRspVectorControlRegisters,ARRAY_SIZE(mipsRspVectorControlRegisters));
+}
+
 bool MipsParser::parseRspVectorRegister(Parser& parser, MipsRegisterValue& dest)
 {
 	dest.type = MipsRegisterType::RspVector;
@@ -1277,6 +1291,9 @@ bool MipsParser::parseParameters(Parser& parser, const tMipsOpcode& opcode)
 			case 'z':	// cop0 register
 				CHECK(parseRspCop0Register(parser,registers.grd));
 				break;
+			case 'c':	// vector control register
+				CHECK(parseRspVectorControlRegister(parser,registers.grd));
+				break;
 			case 't':	// vector register
 				CHECK(parseRspVectorRegister(parser,registers.rspvrt));
 				break;

diff --git a/Archs/MIPS/MipsParser.h b/Archs/MIPS/MipsParser.h
@@ -25,6 +25,7 @@ class MipsParser
 	bool parseCop0Register(Parser& parser, MipsRegisterValue& dest);
 	bool parsePs2Cop2Register(Parser& parser, MipsRegisterValue& dest);
 	bool parseRspCop0Register(Parser& parser, MipsRegisterValue& dest);
+	bool parseRspVectorControlRegister(Parser& parser, MipsRegisterValue& dest);
 	bool parseRspVectorRegister(Parser& parser, MipsRegisterValue& dest);
 	bool parseRspBroadcastElement(Parser& parser, MipsRegisterValue& dest);
 	bool parseRspScalarElement(Parser& parser, MipsRegisterValue& dest);