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clang-tidy: readability-simplify-boolean-expr
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@Kingcom
Kingcom committed Aug 2, 2020
1 parent 1417188 commit 9471890
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Showing 31 changed files with 218 additions and 224 deletions.
4 changes: 2 additions & 2 deletions Archs/ARM/ArmExpressionFunctions.cpp
View file
Expand Up @@ -11,13 +11,13 @@

ExpressionValue expFuncIsArm(const std::wstring& funcName, const std::vector<ExpressionValue>& parameters)
{
bool isArm = Arch == &Arm && Arm.GetThumbMode() == false;
bool isArm = Arch == &Arm && !Arm.GetThumbMode();
return ExpressionValue(isArm ? INT64_C(1) : INT64_C(0));
}

ExpressionValue expFuncIsThumb(const std::wstring& funcName, const std::vector<ExpressionValue>& parameters)
{
bool isThumb = Arm.GetThumbMode() == true;
bool isThumb = Arm.GetThumbMode();
return ExpressionValue(isThumb ? INT64_C(1) : INT64_C(0));
}

Expand Down
28 changes: 14 additions & 14 deletions Archs/ARM/ArmParser.cpp
View file
Expand Up @@ -68,13 +68,13 @@ const wchar_t* msgTemplate =
std::unique_ptr<CAssemblerCommand> parseDirectiveMsg(Parser& parser, int flags)
{
Expression text = parser.parseExpression();
if (text.isLoaded() == false)
if (!text.isLoaded())
return nullptr;

return parser.parseTemplate(msgTemplate, {
{ L"%after%", Global.symbolTable.getUniqueLabelName(true) },
{ L"%text%", text.toString() },
{ L"%alignment%", Arm.GetThumbMode() == true ? L"2" : L"4" }
{ L"%alignment%", Arm.GetThumbMode() ? L"2" : L"4" }
});
}

Expand Down Expand Up @@ -113,7 +113,7 @@ bool ArmParser::parseRegisterTable(Parser& parser, ArmRegisterValue& dest, const

bool ArmParser::parseRegister(Parser& parser, ArmRegisterValue& dest, int max)
{
if (parseRegisterTable(parser,dest,armRegisters,ARRAY_SIZE(armRegisters)) == false)
if (!parseRegisterTable(parser,dest,armRegisters,ARRAY_SIZE(armRegisters)))
return false;

return dest.num <= max;
Expand All @@ -136,14 +136,14 @@ bool ArmParser::parseRegisterList(Parser& parser, int& dest, int validMask)
dest = 0;
while (true)
{
if (parseRegister(parser,reg) == false)
if (!parseRegister(parser,reg))
return false;

if (parser.peekToken().type == TokenType::Minus)
{
parser.eatToken();

if (parseRegister(parser,reg2) == false || reg2.num < reg.num)
if (!parseRegister(parser,reg2) || reg2.num < reg.num)
return false;

for (int i = reg.num; i <= reg2.num; i++)
Expand Down Expand Up @@ -270,7 +270,7 @@ bool ArmParser::parseShift(Parser& parser, ArmOpcodeVariables& vars, bool immedi
{
vars.Shift.ShiftExpression = createConstExpression(number);
vars.Shift.ShiftByRegister = false;
} else if (parseRegister(parser,vars.Shift.reg) == true)
} else if (parseRegister(parser,vars.Shift.reg))
{
if (immediateOnly)
return false;
Expand All @@ -280,7 +280,7 @@ bool ArmParser::parseShift(Parser& parser, ArmOpcodeVariables& vars, bool immedi
if (parser.peekToken().type == TokenType::Hash)
parser.eatToken();

if (parseImmediate(parser,vars.Shift.ShiftExpression) == false)
if (!parseImmediate(parser,vars.Shift.ShiftExpression))
return false;

vars.Shift.ShiftByRegister = false;
Expand All @@ -294,14 +294,14 @@ bool ArmParser::parsePseudoShift(Parser& parser, ArmOpcodeVariables& vars, int t
{
vars.Shift.Type = type;

if (parseRegister(parser,vars.Shift.reg) == true)
if (parseRegister(parser,vars.Shift.reg))
{
vars.Shift.ShiftByRegister = true;
} else {
if (parser.peekToken().type == TokenType::Hash)
parser.eatToken();

if (parseImmediate(parser,vars.Shift.ShiftExpression) == false)
if (!parseImmediate(parser,vars.Shift.ShiftExpression))
return false;

vars.Shift.ShiftByRegister = false;
Expand Down Expand Up @@ -649,11 +649,11 @@ std::unique_ptr<CArmInstruction> ArmParser::parseArmOpcode(Parser& parser)
if ((ArmOpcodes[z].flags & ARM_ARM9) && Arm.getVersion() == AARCH_GBA)
continue;

if (decodeArmOpcode(stringValue,ArmOpcodes[z],vars) == true)
if (decodeArmOpcode(stringValue,ArmOpcodes[z],vars))
{
TokenizerPosition tokenPos = parser.getTokenizer()->getPosition();

if (parseArmParameters(parser,ArmOpcodes[z],vars) == true)
if (parseArmParameters(parser,ArmOpcodes[z],vars))
{
// success, return opcode
return std::make_unique<CArmInstruction>(ArmOpcodes[z],vars);
Expand All @@ -664,7 +664,7 @@ std::unique_ptr<CArmInstruction> ArmParser::parseArmOpcode(Parser& parser)
}
}

if (paramFail == true)
if (paramFail)
parser.printError(token,L"ARM parameter failure");
else
parser.printError(token,L"Invalid ARM opcode");
Expand Down Expand Up @@ -750,7 +750,7 @@ std::unique_ptr<CThumbInstruction> ArmParser::parseThumbOpcode(Parser& parser)
{
TokenizerPosition tokenPos = parser.getTokenizer()->getPosition();

if (parseThumbParameters(parser,ThumbOpcodes[z],vars) == true)
if (parseThumbParameters(parser,ThumbOpcodes[z],vars))
{
// success, return opcode
return std::make_unique<CThumbInstruction>(ThumbOpcodes[z],vars);
Expand All @@ -761,7 +761,7 @@ std::unique_ptr<CThumbInstruction> ArmParser::parseThumbOpcode(Parser& parser)
}
}

if (paramFail == true)
if (paramFail)
parser.printError(token,L"THUMB parameter failure in %S",stringValue);
else
parser.printError(token,L"Invalid THUMB opcode: %S",stringValue);
Expand Down
52 changes: 26 additions & 26 deletions Archs/ARM/CArmInstruction.cpp
View file
Expand Up @@ -71,9 +71,9 @@ bool CArmInstruction::Validate(const ValidateState &state)
Logger::queueError(Logger::Warning,L"Opcode not word aligned");
}

if (Vars.Shift.UseShift == true && Vars.Shift.ShiftByRegister == false)
if (Vars.Shift.UseShift && !Vars.Shift.ShiftByRegister)
{
if (Vars.Shift.ShiftExpression.evaluateInteger(Vars.Shift.ShiftAmount) == false)
if (!Vars.Shift.ShiftExpression.evaluateInteger(Vars.Shift.ShiftAmount))
{
Logger::queueError(Logger::Error,L"Invalid expression");
return false;
Expand Down Expand Up @@ -115,7 +115,7 @@ bool CArmInstruction::Validate(const ValidateState &state)

if (Opcode.flags & ARM_COPOP)
{
if (Vars.CopData.CpopExpression.evaluateInteger(Vars.CopData.Cpop) == false)
if (!Vars.CopData.CpopExpression.evaluateInteger(Vars.CopData.Cpop))
{
Logger::queueError(Logger::Error,L"Invalid expression");
return false;
Expand All @@ -130,7 +130,7 @@ bool CArmInstruction::Validate(const ValidateState &state)

if (Opcode.flags & ARM_COPINF)
{
if (Vars.CopData.CpinfExpression.evaluateInteger(Vars.CopData.Cpinf) == false)
if (!Vars.CopData.CpinfExpression.evaluateInteger(Vars.CopData.Cpinf))
{
Logger::queueError(Logger::Error,L"Invalid expression");
return false;
Expand Down Expand Up @@ -324,7 +324,7 @@ void CArmInstruction::FormatOpcode(char* Dest, const char* Source) const
Source++;
break;
case 'S': // set flag
if (Vars.Opcode.s == true) *Dest++ = 's';
if (Vars.Opcode.s) *Dest++ = 's';
Source++;
break;
case 'A': // addressing mode
Expand All @@ -337,12 +337,12 @@ void CArmInstruction::FormatOpcode(char* Dest, const char* Source) const
Source++;
break;
case 'X': // x flag
if (Vars.Opcode.x == false) *Dest++ = 'b';
if (!Vars.Opcode.x) *Dest++ = 'b';
else *Dest++ = 't';
Source++;
break;
case 'Y': // y flag
if (Vars.Opcode.y == false) *Dest++ = 'b';
if (!Vars.Opcode.y) *Dest++ = 'b';
else *Dest++ = 't';
Source++;
break;
Expand Down Expand Up @@ -471,14 +471,14 @@ void CArmInstruction::writeTempData(TempData& tempData) const

void CArmInstruction::Encode() const
{
unsigned int encoding = Vars.Opcode.UseNewEncoding == true ? Vars.Opcode.NewEncoding : Opcode.encoding;
unsigned int encoding = Vars.Opcode.UseNewEncoding ? Vars.Opcode.NewEncoding : Opcode.encoding;

if ((Opcode.flags & ARM_UNCOND) == 0) encoding |= Vars.Opcode.c << 28;
if (Vars.Opcode.s == true) encoding |= (1 << 20);
if (Vars.Opcode.s) encoding |= (1 << 20);

unsigned char shiftType;
int shiftAmount;
if (Vars.Shift.UseFinal == true)
if (Vars.Shift.UseFinal)
{
shiftType = Vars.Shift.FinalType;
shiftAmount = Vars.Shift.FinalShiftAmount;
Expand All @@ -487,7 +487,7 @@ void CArmInstruction::Encode() const
shiftAmount = Vars.Shift.ShiftAmount;
}

switch (Vars.Opcode.UseNewType == true ? Vars.Opcode.NewType : Opcode.type)
switch (Vars.Opcode.UseNewType ? Vars.Opcode.NewType : Opcode.type)
{
case ARM_TYPE3: // ARM.3: Branch and Exchange (BX, BLX)
encoding |= (Vars.rn.num << 0);
Expand All @@ -505,9 +505,9 @@ void CArmInstruction::Encode() const
encoding |= (shiftAmount << 7);
encoding |= Vars.Immediate;
} else if (Opcode.flags & ARM_REGISTER) { // shifted register als op2
if (Vars.Shift.UseShift == true)
if (Vars.Shift.UseShift)
{
if (Vars.Shift.ShiftByRegister == true)
if (Vars.Shift.ShiftByRegister)
{
encoding |= (Vars.Shift.reg.num << 8);
encoding |= (1 << 4);
Expand All @@ -522,10 +522,10 @@ void CArmInstruction::Encode() const
case ARM_TYPE6: // ARM.6: PSR Transfer (MRS, MSR)
if (Opcode.flags & ARM_MRS) // MRS{cond} Rd,Psr ;Rd = Psr
{
if (Vars.PsrData.spsr == true) encoding |= (1 << 22);
if (Vars.PsrData.spsr) encoding |= (1 << 22);
encoding |= (Vars.rd.num << 12);
} else { // MSR{cond} Psr{_field},Op ;Psr[field] = Op
if (Vars.PsrData.spsr == true) encoding |= (1 << 22);
if (Vars.PsrData.spsr) encoding |= (1 << 22);
encoding |= (Vars.PsrData.field << 16);

if (Opcode.flags & ARM_REGISTER)
Expand All @@ -542,16 +542,16 @@ void CArmInstruction::Encode() const
encoding |= (Vars.rd.num << 16);
if (Opcode.flags & ARM_N) encoding |= (Vars.rn.num << 12);
encoding |= (Vars.rs.num << 8);
if ((Opcode.flags & ARM_Y) && Vars.Opcode.y == true) encoding |= (1 << 6);
if ((Opcode.flags & ARM_X) && Vars.Opcode.x == true) encoding |= (1 << 5);
if ((Opcode.flags & ARM_Y) && Vars.Opcode.y) encoding |= (1 << 6);
if ((Opcode.flags & ARM_X) && Vars.Opcode.x) encoding |= (1 << 5);
encoding |= (Vars.rm.num << 0);
break;
case ARM_TYPE9: // ARM.9: Single Data Transfer (LDR, STR, PLD)
if (Vars.writeback == true) encoding |= (1 << 21);
if (Vars.writeback) encoding |= (1 << 21);
if (Opcode.flags & ARM_N) encoding |= (Vars.rn.num << 16);
if (Opcode.flags & ARM_D) encoding |= (Vars.rd.num << 12);
if ((Opcode.flags & ARM_SIGN) && Vars.SignPlus == false) encoding &= ~(1 << 23);
if ((Opcode.flags & ARM_ABS) && Vars.negative == true) encoding &= ~(1 << 23);
if ((Opcode.flags & ARM_SIGN) && !Vars.SignPlus) encoding &= ~(1 << 23);
if ((Opcode.flags & ARM_ABS) && Vars.negative) encoding &= ~(1 << 23);
if (Opcode.flags & ARM_IMMEDIATE)
{
int immediate = Vars.Immediate;
Expand All @@ -563,7 +563,7 @@ void CArmInstruction::Encode() const
encoding |= (immediate << 0);
} else if (Opcode.flags & ARM_REGISTER) // ... means the opcocde uses shifts with immediates
{
if (Vars.Shift.UseShift == true)
if (Vars.Shift.UseShift)
{
encoding |= (shiftAmount << 7);
encoding |= (shiftType << 5);
Expand All @@ -572,11 +572,11 @@ void CArmInstruction::Encode() const
}
break;
case ARM_TYPE10: // ARM.10: Halfword, Doubleword, and Signed Data Transfer
if (Vars.writeback == true) encoding |= (1 << 21);
if (Vars.writeback) encoding |= (1 << 21);
encoding |= (Vars.rn.num << 16);
encoding |= (Vars.rd.num << 12);
if ((Opcode.flags & ARM_SIGN) && Vars.SignPlus == false) encoding &= ~(1 << 23);
if ((Opcode.flags & ARM_ABS) && Vars.negative == true) encoding &= ~(1 << 23);
if ((Opcode.flags & ARM_SIGN) && !Vars.SignPlus) encoding &= ~(1 << 23);
if ((Opcode.flags & ARM_ABS) && Vars.negative) encoding &= ~(1 << 23);
if (Opcode.flags & ARM_IMMEDIATE)
{
int immediate = Vars.Immediate;
Expand All @@ -595,8 +595,8 @@ void CArmInstruction::Encode() const
case ARM_TYPE11: // ARM.11: Block Data Transfer (LDM,STM)
if (Opcode.flags & ARM_LOAD) encoding |= (LdmModes[Vars.Opcode.a] << 23);
else if (Opcode.flags & ARM_STORE) encoding |= (StmModes[Vars.Opcode.a] << 23);
if (Vars.psr == true) encoding |= (1 << 22);
if (Vars.writeback == true) encoding |= (1 << 21);
if (Vars.psr) encoding |= (1 << 22);
if (Vars.writeback) encoding |= (1 << 21);
if (Opcode.flags & ARM_N) encoding |= (Vars.rn.num << 16);
encoding |= (Vars.rlist);
break;
Expand Down
2 changes: 1 addition & 1 deletion Archs/ARM/Pool.cpp
View file
Expand Up @@ -26,7 +26,7 @@ void ArmStateCommand::writeSymData(SymbolData& symData) const
if (RamPos == -1)
return;

if (armstate == true)
if (armstate)
{
symData.addLabel(RamPos,L".arm");
} else {
Expand Down
14 changes: 7 additions & 7 deletions Archs/MIPS/CMipsInstruction.cpp
View file
Expand Up @@ -101,7 +101,7 @@ bool CMipsInstruction::Validate(const ValidateState &state)
{
if (immediateData.primary.expression.isLoaded())
{
if (immediateData.primary.expression.evaluateInteger(immediateData.primary.value) == false)
if (!immediateData.primary.expression.evaluateInteger(immediateData.primary.value))
{
Logger::queueError(Logger::Error, L"Invalid immediate expression");
return false;
Expand Down Expand Up @@ -172,7 +172,7 @@ bool CMipsInstruction::Validate(const ValidateState &state)
{
if (immediateData.secondary.expression.isLoaded())
{
if (immediateData.secondary.expression.evaluateInteger(immediateData.secondary.value) == false)
if (!immediateData.secondary.expression.evaluateInteger(immediateData.secondary.value))
{
Logger::queueError(Logger::Error, L"Invalid immediate expression");
return false;
Expand Down Expand Up @@ -209,7 +209,7 @@ bool CMipsInstruction::Validate(const ValidateState &state)
}

// check load delay
if (Mips.hasLoadDelay() && Mips.GetLoadDelay() && IgnoreLoadDelay == false)
if (Mips.hasLoadDelay() && Mips.GetLoadDelay() && !IgnoreLoadDelay)
{
bool fix = false;

Expand All @@ -228,23 +228,23 @@ bool CMipsInstruction::Validate(const ValidateState &state)
fix = true;
}

if (Mips.GetFixLoadDelay() == true && fix == true)
if (Mips.GetFixLoadDelay() && fix)
{
addNop = true;
Logger::queueError(Logger::Notice,L"added nop to ensure correct behavior");
}
}

if ((opcodeData.opcode.flags & MO_NODELAYSLOT) && Mips.GetDelaySlot() == true && IgnoreLoadDelay == false)
if ((opcodeData.opcode.flags & MO_NODELAYSLOT) && Mips.GetDelaySlot() && !IgnoreLoadDelay)
{
Logger::queueError(Logger::Error,L"This instruction can't be in a delay slot");
}

Mips.SetDelaySlot(opcodeData.opcode.flags & MO_DELAY ? true : false);
Mips.SetDelaySlot((opcodeData.opcode.flags & MO_DELAY) != 0);

// now check if this opcode causes a load delay
if (Mips.hasLoadDelay())
Mips.SetLoadDelay(opcodeData.opcode.flags & MO_DELAYRT ? true : false,registerData.grt.num);
Mips.SetLoadDelay((opcodeData.opcode.flags & MO_DELAYRT) != 0,registerData.grt.num);

if (previousNop != addNop)
Result = true;
Expand Down
6 changes: 3 additions & 3 deletions Archs/MIPS/MipsElfFile.cpp
View file
Expand Up @@ -202,7 +202,7 @@ bool MipsElfFile::load(const std::wstring& fileName, const std::wstring& outputF
{
this->outputFileName = outputFileName;

if (elf.load(fileName,true) == false)
if (!elf.load(fileName,true))
{
Logger::printError(Logger::FatalError,L"Failed to load %s",fileName);
return false;
Expand Down Expand Up @@ -270,7 +270,7 @@ DirectiveLoadMipsElf::DirectiveLoadMipsElf(const std::wstring& fileName)
file = std::make_shared<MipsElfFile>();

this->inputName = getFullPathName(fileName);
if (file->load(this->inputName,this->inputName) == false)
if (!file->load(this->inputName,this->inputName))
{
file = nullptr;
return;
Expand All @@ -285,7 +285,7 @@ DirectiveLoadMipsElf::DirectiveLoadMipsElf(const std::wstring& inputName, const

this->inputName = getFullPathName(inputName);
this->outputName = getFullPathName(outputName);
if (file->load(this->inputName,this->outputName) == false)
if (!file->load(this->inputName,this->outputName))
{
file = nullptr;
return;
Expand Down
2 changes: 1 addition & 1 deletion Archs/MIPS/MipsMacros.cpp
View file
Expand Up @@ -26,7 +26,7 @@ bool MipsMacroCommand::Validate(const ValidateState &state)

applyFileInfo();

if (IgnoreLoadDelay == false && Mips.GetDelaySlot() == true && (newMemoryPos-memoryPos) > 4
if (!IgnoreLoadDelay && Mips.GetDelaySlot() && (newMemoryPos-memoryPos) > 4
&& (macroFlags & MIPSM_DONTWARNDELAYSLOT) == 0)
{
Logger::queueError(Logger::Warning,L"Macro with multiple opcodes used inside a delay slot");
Expand Down

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