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Bliss-Box Low Latency API Implementation in SystemVerilog
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Failed to load latest commit information. rework for updated Serial IO standards in sys Feb 28, 2019 initial commit Feb 22, 2019

Low Latency API

This is a SystemVerilog module for use with the two-wire Bliss-Box low latency API, primarily for MiSTer. Information about the file's use can be found at the top of the code.

More information can be found at Bliss-Box's homepage.

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