Pulse generator (#203)

* add pulse_generator core

* edit pulse generator test_bench

fpga/cores/pulse_generator_v1_0/core_config.tcl

@@ -0,0 +1,10 @@
+set display_name {Pulse generator}
+
+set core [ipx::current_core]
+
+set_property DISPLAY_NAME $display_name $core
+set_property DESCRIPTION $display_name $core
+
+set_property VENDOR {koheron} $core
+set_property VENDOR_DISPLAY_NAME {Koheron} $core
+set_property COMPANY_URL {http://www.koheron.com} $core

fpga/cores/pulse_generator_v1_0/pulse_generator.v

@@ -0,0 +1,40 @@
+`timescale 1 ns / 1 ps
+
+module pulse_generator #
+(
+  parameter integer PULSE_WIDTH_WIDTH = 8,
+  parameter integer PULSE_PERIOD_WIDTH = 16
+)
+(
+  input wire clk,
+  input wire [PULSE_WIDTH_WIDTH-1:0] pulse_width,
+  input wire [PULSE_PERIOD_WIDTH-1:0] pulse_period,
+  input wire rst,
+  output reg dout
+);
+
+reg [PULSE_WIDTH_WIDTH-1:0] pulse_width_reg;
+reg [PULSE_PERIOD_WIDTH-1:0] pulse_period_reg;
+reg [PULSE_PERIOD_WIDTH-1:0] cnt;
+initial cnt = 0;
+
+always @(posedge clk) begin
+  pulse_width_reg <= pulse_width;
+  pulse_period_reg <= pulse_period;
+end
+
+
+always @(posedge clk) begin
+  dout <= (cnt < pulse_width_reg);
+  if (rst) begin
+    cnt <= 0;
+  end else begin
+    if (cnt < pulse_period_reg - 1) begin
+      cnt <= cnt + 1;
+    end else begin
+      cnt <= 0;      
+    end
+  end
+end
+
+endmodule

fpga/cores/pulse_generator_v1_0/pulse_generator_tb.v

@@ -0,0 +1,46 @@
+`timescale 1 ns / 1 ps
+
+module pulse_generator_tb();
+
+  parameter integer PULSE_WIDTH_WIDTH = 8;
+  parameter integer PULSE_PERIOD_WIDTH = 16;
+
+  reg clk;
+  reg [PULSE_WIDTH_WIDTH-1:0] pulse_width;
+  reg [PULSE_PERIOD_WIDTH-1:0] pulse_period;
+  reg rst;
+  wire dout;
+
+  pulse_generator #(
+    .PULSE_WIDTH_WIDTH(PULSE_WIDTH_WIDTH),
+    .PULSE_PERIOD_WIDTH(PULSE_PERIOD_WIDTH)
+  )
+  DUT (
+    .clk(clk),
+    .pulse_width(pulse_width),
+    .pulse_period(pulse_period),
+    .rst(rst),
+    .dout(dout)
+  );
+
+  parameter CLK_PERIOD = 8;
+
+  always #(CLK_PERIOD/2) clk = ~clk;
+
+  initial begin
+    clk = 1'b1;
+    pulse_width = 10;
+    pulse_period = 100;
+    rst = 0;
+    #(166*CLK_PERIOD)
+    rst = 1;
+    #(CLK_PERIOD)
+    rst = 0;
+    #(1000*CLK_PERIOD)
+    pulse_period = 50;
+    pulse_width = 25;
+    #(100000*CLK_PERIOD)
+    $finish;
+  end
+
+endmodule