board: rockchip: Add Pine64 PineTab2

Tested with a Pine64 PineTab2 v2.0:
- SD-card boot
- eMMC boot
- SPI Flash boot
- USB host

Device tree imported from v6.4.3-danctnix1

The generated u-boot-rockchip.bin image contain idbloader.img and
u-boot.itb at the expected offset and should be written to sector 64
of a SD-card or on-board eMMC.

The generated u-boot-rockchip-spi.bin should be written to 0x0 of
SPI Flash, the spi image use following offsets:
- 0x8000: idbloader.img (TPL + SPL)
- 0x60000: u-boot.itb (FIT image for U-Boot)

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>

arch/arm/dts/Makefile

@@ -171,6 +171,8 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
 
 dtb-$(CONFIG_ROCKCHIP_RK3568) += \
 	rk3566-anbernic-rgxx3.dtb \
+	rk3566-pinetab2-v0.1.dtb \
+	rk3566-pinetab2-v2.0.dtb \
 	rk3566-quartz64-a.dtb \
 	rk3566-quartz64-b.dtb \
 	rk3566-radxa-cm3-io.dtb \

arch/arm/dts/rk3566-pinetab2-u-boot.dtsi

@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include "rk356x-u-boot.dtsi"
+
+/ {
+	chosen {
+		stdout-path = &uart2;
+	};
+};
+
+&cru {
+	assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
+	assigned-clock-rates = <32768>, <1200000000>, <200000000>, <500000000>;
+	assigned-clock-parents = <&pmucru CLK_RTC32K_FRAC>;
+};
+
+&fspi_dual_io_pins {
+	bootph-all;
+};
+
+&gpio0 {
+	bootph-all;
+};
+
+&i2c0 {
+	bootph-pre-ram;
+};
+
+&rk817 {
+	bootph-pre-ram;
+
+	regulators {
+		bootph-pre-ram;
+	};
+};
+
+&sdhci {
+	cap-mmc-highspeed;
+	mmc-ddr-1_8v;
+};
+
+&sdmmc_pwren_l {
+	bootph-all;
+};
+
+&sfc {
+	bootph-pre-ram;
+	u-boot,spl-sfc-no-dma;
+
+	flash@0 {
+		bootph-pre-ram;
+	};
+};
+
+&uart2 {
+	bootph-all;
+	clock-frequency = <24000000>;
+	status = "okay";
+};
+
+&vcc3v3_sd {
+	bootph-pre-ram;
+};

arch/arm/dts/rk3566-pinetab2-v0.1-u-boot.dtsi

@@ -0,0 +1,3 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include "rk3566-pinetab2-u-boot.dtsi"

arch/arm/dts/rk3566-pinetab2-v0.1.dts

@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include "rk3566-pinetab2.dtsi"
+
+/ {
+	model = "Pine64 PineTab2 v0.1";
+	compatible = "pine64,pinetab2-v0.1", "pine64,pinetab2", "rockchip,rk3566";
+};
+
+&lcd {
+	reset-gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>;
+};
+
+&pinctrl {
+	display {
+		lcd0_rst_l: lcd0-rst-l {
+			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&vcc_wl {
+	gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
+};

arch/arm/dts/rk3566-pinetab2-v2.0-u-boot.dtsi

@@ -0,0 +1,3 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include "rk3566-pinetab2-u-boot.dtsi"

arch/arm/dts/rk3566-pinetab2-v2.0.dts

@@ -0,0 +1,46 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include "rk3566-pinetab2.dtsi"
+
+/ {
+	model = "Pine64 PineTab2 v2.0";
+	compatible = "pine64,pinetab2-v2.0", "pine64,pinetab2", "rockchip,rk3566";
+};
+
+&gpio_keys {
+	pinctrl-0 = <&kb_id_det>, <&hall_int_l>;
+
+	hall-sensor {
+		debounce-interval = <20>;
+		gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>;
+		label = "Hall Sensor";
+		linux,code = <SW_LID>;
+		linux,input-type = <EV_SW>;
+		wakeup-event-action = <EV_ACT_DEASSERTED>;
+		wakeup-source;
+	};
+};
+
+&lcd {
+	reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_LOW>;
+};
+
+&pinctrl {
+	display {
+		lcd0_rst_l: lcd0-rst-l {
+			rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	hall {
+		hall_int_l: hall-int-l {
+			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&vcc_wl {
+	gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
+};