HACK: rk3566-quartz64-b: Use UART5 as serial console

Regular UART2 pins is not fully working on v1.4 boards, use UART5 as serial console instead: - pin 32: uart5_tx_m1 - pin 33: uart5_rx_m1 Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Kwiboo · Oct 11, 2023 · dcdedd1 · dcdedd1
1 parent ef68159
commit dcdedd1
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Showing 3 changed files with 114 additions and 3 deletions.
diff --git a/arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi b/arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi
@@ -4,7 +4,13 @@
 
 / {
 	chosen {
+#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xfe660000)
 		stdout-path = &uart2;
+#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xfe690000)
+		stdout-path = &uart5;
+#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xfe6d0000)
+		stdout-path = &uart9;
+#endif
 	};
 };
 
@@ -30,6 +36,38 @@
 	status = "okay";
 };
 
+#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xfe690000)
+/*
+ * uart5_m1 is exposed on PI40
+ * pin 32 - uart5_tx_m1
+ * pin 33 - uart5_rx_m1
+ */
+&uart5m1_xfer {
+	bootph-all;
+};
+&uart5 {
+	bootph-all;
+	clock-frequency = <24000000>;
+	pinctrl-0 = <&uart5m1_xfer>;
+	status = "okay";
+};
+#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xfe6d0000)
+/*
+ * uart9_m1 is exposed on PI40
+ * pin 21 - uart9_tx_m1
+ * pin 24 - uart9_rx_m1
+ */
+&uart9m1_xfer {
+	bootph-all;
+};
+&uart9 {
+	bootph-all;
+	clock-frequency = <24000000>;
+	pinctrl-0 = <&uart9m1_xfer>;
+	status = "okay";
+};
+#endif
+
 &usb_host0_xhci {
 	dr_mode = "host";
 };

diff --git a/arch/arm/mach-rockchip/rk3568/rk3568.c b/arch/arm/mach-rockchip/rk3568/rk3568.c
@@ -34,8 +34,8 @@
 #define CPU_GRF_BASE		0xfdc30000
 #define GRF_CORE_PVTPLL_CON0	(0x10)
 
-/* PMU_GRF_GPIO0D_IOMUX_L */
 enum {
+	/* PMU_GRF_GPIO0D_IOMUX_L */
 	GPIO0D1_SHIFT		= 4,
 	GPIO0D1_MASK		= GENMASK(6, 4),
 	GPIO0D1_GPIO		= 0,
@@ -47,11 +47,62 @@ enum {
 	GPIO0D0_UART2_RXM0,
 };
 
-/* GRF_IOFUNC_SEL3 */
 enum {
+	/* GRF_GPIO3C_IOMUX_L */
+	GPIO3C3_SHIFT		= 12,
+	GPIO3C3_MASK		= GENMASK(14, 12),
+	GPIO3C3_GPIO		= 0,
+	GPIO3C3_LCDC_DEN,
+	GPIO3C3_BT1120_D15,
+	GPIO3C3_SPI1_CLKM1,
+	GPIO3C3_UART5_RXM1,
+	GPIO3C3_I2S1_SCLKRXM,
+
+	GPIO3C2_SHIFT		= 8,
+	GPIO3C2_MASK		= GENMASK(10, 8),
+	GPIO3C2_GPIO		= 0,
+	GPIO3C2_LCDC_VSYNC,
+	GPIO3C2_BT1120_D14,
+	GPIO3C2_SPI1_MISOM1,
+	GPIO3C2_UART5_TXM1,
+	GPIO3C2_I2S1_SDO3M2,
+
+	/* GRF_GPIO4C_IOMUX_H */
+	GPIO4C6_SHIFT		= 8,
+	GPIO4C6_MASK		= GENMASK(10, 8),
+	GPIO4C6_GPIO		= 0,
+	GPIO4C6_PWM13_M1,
+	GPIO4C6_SPI3_CS0M1,
+	GPIO4C6_SATA0_ACTLED,
+	GPIO4C6_UART9_RXM1,
+	GPIO4C6_I2S3_SDIM1,
+
+	GPIO4C5_SHIFT		= 4,
+	GPIO4C5_MASK		= GENMASK(6, 4),
+	GPIO4C5_GPIO		= 0,
+	GPIO4C5_PWM12_M1,
+	GPIO4C5_SPI3_MISOM1,
+	GPIO4C5_SATA1_ACTLED,
+	GPIO4C5_UART9_TXM1,
+	GPIO4C5_I2S3_SDOM1,
+
+	/* GRF_IOFUNC_SEL3 */
 	UART2_IO_SEL_SHIFT	= 10,
 	UART2_IO_SEL_MASK	= GENMASK(11, 10),
 	UART2_IO_SEL_M0		= 0,
+	UART2_IO_SEL_M1,
+
+	/* GRF_IOFUNC_SEL4 */
+	UART9_IO_SEL_SHIFT	= 8,
+	UART9_IO_SEL_MASK	= GENMASK(9, 8),
+	UART9_IO_SEL_M0		= 0,
+	UART9_IO_SEL_M1,
+	UART9_IO_SEL_M2,
+
+	UART5_IO_SEL_SHIFT	= 0,
+	UART5_IO_SEL_MASK	= GENMASK(0, 0),
+	UART5_IO_SEL_M0		= 0,
+	UART5_IO_SEL_M1,
 };
 
 static struct mm_region rk3568_mem_map[] = {
@@ -94,6 +145,7 @@ void board_debug_uart_init(void)
 	static struct rk3568_pmugrf * const pmugrf = (void *)PMUGRF_BASE;
 	static struct rk3568_grf * const grf = (void *)GRF_BASE;
 
+#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xfe660000)
 	/* UART2 M0 */
 	rk_clrsetreg(&grf->iofunc_sel3, UART2_IO_SEL_MASK,
 		     UART2_IO_SEL_M0 << UART2_IO_SEL_SHIFT);
@@ -103,6 +155,27 @@ void board_debug_uart_init(void)
 		     GPIO0D1_MASK | GPIO0D0_MASK,
 		     GPIO0D1_UART2_TXM0 << GPIO0D1_SHIFT |
 		     GPIO0D0_UART2_RXM0 << GPIO0D0_SHIFT);
+#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xfe690000)
+	/* UART5 M1 */
+	rk_clrsetreg(&grf->iofunc_sel4, UART5_IO_SEL_MASK,
+		     UART5_IO_SEL_M1 << UART5_IO_SEL_SHIFT);
+
+	/* Switch iomux */
+	rk_clrsetreg(&grf->gpio3c_iomux_l,
+		     GPIO3C3_MASK | GPIO3C2_MASK,
+		     GPIO3C3_UART5_RXM1 << GPIO3C3_SHIFT |
+		     GPIO3C2_UART5_TXM1 << GPIO3C2_SHIFT);
+#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xfe6d0000)
+	/* UART9 M1 */
+	rk_clrsetreg(&grf->iofunc_sel4, UART9_IO_SEL_MASK,
+		     UART9_IO_SEL_M1 << UART9_IO_SEL_SHIFT);
+
+	/* Switch iomux */
+	rk_clrsetreg(&grf->gpio4c_iomux_h,
+		     GPIO4C6_MASK | GPIO4C5_MASK,
+		     GPIO4C6_UART9_RXM1 << GPIO4C6_SHIFT |
+		     GPIO4C5_UART9_TXM1 << GPIO4C5_SHIFT);
+#endif
 }
 
 int arch_cpu_init(void)

diff --git a/configs/quartz64-b-rk3566_defconfig b/configs/quartz64-b-rk3566_defconfig
@@ -18,7 +18,7 @@ CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK_R_ADDR=0x600000
 CONFIG_TARGET_QUARTZ64_RK3566=y
 CONFIG_SPL_STACK=0x400000
-CONFIG_DEBUG_UART_BASE=0xFE660000
+CONFIG_DEBUG_UART_BASE=0xFE690000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y