Seoul National University EE computer organization lecture. by prof.JangWoo Kim
The whole purpose of this project is to complete a system. To do this, I built a pipeline CPU with cache and DMA added starting with a single cycle CPU.
You can find Verilog source code in 'some_project_folder/project_folder.srcs/sources_1/imports/code'
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ALU : 16-bit ALU
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RTL sequential logic
2-1) 010 detector
2-2) Register File
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Vending machine : RTL Design
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16-bit single cycle CPU
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16-bit multi cycle CPU
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16-bit pipeline CPU
6-1) pipeline CPU with stall for data hazard solution
6-2) pipeline CPU with forwarding for data hazard solution
6-3) pipeline CPU with branch predictor for control hazard solution
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16-bit pipeline CPU with cache
7-1) baseline CPU - it takes 2-cycle to read memory
7-2) cache CPU - it takes 6-cycle to read memory and 1-cycle to read cache
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16-bit pipeline CPU with DMA controller
Externel Device write data to memory. DMA controller can handle this without CPU stall
8-1) DMA controller
8-2) DMA controller with cycle stealing
You can enter some project folder and open description file. Just press 'run simulation' button to test projects.
I leave this project for my juniors. Good Luck!