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A repo where i keep track of my progress trying to learn the verilog HDL.

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Name		Name	Last commit message	Last commit date
Latest commit History 5 Commits
.vscode		.vscode
Combinational Examples		Combinational Examples
UART		UART
fsm_practice		fsm_practice
seq_practice		seq_practice
README.md		README.md

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verilog-stuff

A repo where i keep track of my progress trying to learn the verilog HDL.

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A repo where i keep track of my progress trying to learn the verilog HDL.

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