Verilog_Design

This repos is for studying Verilog HDL

Studying Digital design course

Name		Name	Last commit message	Last commit date
Latest commit History 13 Commits
1bit_comparator		1bit_comparator
2x4decoder_enable		2x4decoder_enable
3x8_decoder		3x8_decoder
4_bit_adder		4_bit_adder
4bit_comparator		4bit_comparator
4to1_MUX		4to1_MUX
4x2_MUX		4x2_MUX
4x2_encoder_prority		4x2_encoder_prority
8bit_adder_substractor		8bit_adder_substractor
8x3_encoder		8x3_encoder
Digital_clock		Digital_clock
Flip_Flop		Flip_Flop
Latch		Latch
and_gate		and_gate
full_adder		full_adder
full_substractor		full_substractor
half_adder		half_adder
sync_counter		sync_counter
triState_2to4MUX		triState_2to4MUX
README.md		README.md

LEE-JAE-HYUN179/Verilog_Design