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drm/msm/a5xx: Add support for Adreno 505 GPU
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@Lanik123
Lanik123 committed Nov 12, 2023
1 parent bd88958 commit 311381b
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Showing 3 changed files with 39 additions and 12 deletions.
29 changes: 17 additions & 12 deletions drivers/gpu/drm/msm/adreno/a5xx_gpu.c
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Original file line number Diff line number Diff line change
Expand Up @@ -439,7 +439,8 @@ void a5xx_set_hwcg(struct msm_gpu *gpu, bool state)
const struct adreno_five_hwcg_regs *regs;
unsigned int i, sz;

if (adreno_is_a506(adreno_gpu) || adreno_is_a508(adreno_gpu)) {
if (adreno_is_a505(adreno_gpu) || adreno_is_a506(adreno_gpu) ||
adreno_is_a508(adreno_gpu)) {
regs = a50x_hwcg;
sz = ARRAY_SIZE(a50x_hwcg);
} else if (adreno_is_a509(adreno_gpu) || adreno_is_a512(adreno_gpu)) {
Expand Down Expand Up @@ -483,7 +484,8 @@ static int a5xx_me_init(struct msm_gpu *gpu)
OUT_RING(ring, 0x00000000);

/* Specify workarounds for various microcode issues */
if (adreno_is_a506(adreno_gpu) || adreno_is_a530(adreno_gpu)) {
if (adreno_is_a505(adreno_gpu) || adreno_is_a506(adreno_gpu) ||
adreno_is_a530(adreno_gpu)) {
/* Workaround for token end syncs
* Force a WFI after every direct-render 3D mode draw and every
* 2D mode 3 draw
Expand Down Expand Up @@ -752,10 +754,11 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
0x00100000 + adreno_gpu->info->gmem - 1);
gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MAX_HI, 0x00000000);

if (adreno_is_a506(adreno_gpu) || adreno_is_a508(adreno_gpu) ||
adreno_is_a510(adreno_gpu)) {
if (adreno_is_a505(adreno_gpu) || adreno_is_a506(adreno_gpu) ||
adreno_is_a508(adreno_gpu) || adreno_is_a510(adreno_gpu)) {
gpu_write(gpu, REG_A5XX_CP_MEQ_THRESHOLDS, 0x20);
if (adreno_is_a506(adreno_gpu) || adreno_is_a508(adreno_gpu))
if (adreno_is_a505(adreno_gpu) || adreno_is_a506(adreno_gpu) ||
adreno_is_a508(adreno_gpu))
gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x400);
else
gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x20);
Expand All @@ -771,7 +774,8 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_1, 0x40201B16);
}

if (adreno_is_a506(adreno_gpu) || adreno_is_a508(adreno_gpu))
if (adreno_is_a505(adreno_gpu) || adreno_is_a506(adreno_gpu) ||
adreno_is_a508(adreno_gpu))
gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL,
(0x100 << 11 | 0x100 << 22));
else if (adreno_is_a509(adreno_gpu) || adreno_is_a510(adreno_gpu) ||
Expand All @@ -789,8 +793,9 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
* Disable the RB sampler datapath DP2 clock gating optimization
* for 1-SP GPUs, as it is enabled by default.
*/
if (adreno_is_a506(adreno_gpu) || adreno_is_a508(adreno_gpu) ||
adreno_is_a509(adreno_gpu) || adreno_is_a512(adreno_gpu))
if (adreno_is_a505(adreno_gpu) || adreno_is_a506(adreno_gpu) ||
adreno_is_a508(adreno_gpu) || adreno_is_a509(adreno_gpu) ||
adreno_is_a512(adreno_gpu))
gpu_rmw(gpu, REG_A5XX_RB_DBG_ECO_CNTL, 0, (1 << 9));

/* Disable UCHE global filter as SP can invalidate/flush independently */
Expand Down Expand Up @@ -1348,7 +1353,7 @@ static int a5xx_pm_resume(struct msm_gpu *gpu)
if (ret)
return ret;

/* Adreno 506, 508, 509, 510, 512 needs manual RBBM sus/res control */
/* Adreno 505, 506, 508, 509, 510, 512 needs manual RBBM sus/res control */
if (!(adreno_is_a530(adreno_gpu) || adreno_is_a540(adreno_gpu))) {
/* Halt the sp_input_clk at HM level */
gpu_write(gpu, REG_A5XX_RBBM_CLOCK_CNTL, 0x00000055);
Expand Down Expand Up @@ -1391,9 +1396,9 @@ static int a5xx_pm_suspend(struct msm_gpu *gpu)
u32 mask = 0xf;
int i, ret;

/* A506, A508, A510 have 3 XIN ports in VBIF */
if (adreno_is_a506(adreno_gpu) || adreno_is_a508(adreno_gpu) ||
adreno_is_a510(adreno_gpu))
/* A505, A506, A508, A510 have 3 XIN ports in VBIF */
if (adreno_is_a505(adreno_gpu) || adreno_is_a506(adreno_gpu) ||
adreno_is_a508(adreno_gpu) || adreno_is_a510(adreno_gpu))
mask = 0x7;

/* Clear the VBIF pipe before shutting down */
Expand Down
17 changes: 17 additions & 0 deletions drivers/gpu/drm/msm/adreno/adreno_device.c
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Original file line number Diff line number Diff line change
Expand Up @@ -142,6 +142,23 @@ static const struct adreno_info gpulist[] = {
.gmem = (SZ_1M + SZ_512K),
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
.init = a4xx_gpu_init,
}, {
.chip_ids = ADRENO_CHIP_IDS(0x05000500),
.family = ADRENO_5XX,
.revn = 505,
.fw = {
[ADRENO_FW_PM4] = "a530_pm4.fw",
[ADRENO_FW_PFP] = "a530_pfp.fw",
},
.gmem = (SZ_128K + SZ_8K),
/*
* Increase inactive period to 250 to avoid bouncing
* the GDSC which appears to make it grumpy
*/
.inactive_period = 250,
.quirks = ADRENO_QUIRK_TWO_PASS_USE_WFI |
ADRENO_QUIRK_LMLOADKILL_DISABLE,
.init = a5xx_gpu_init,
}, {
.chip_ids = ADRENO_CHIP_IDS(0x05000600),
.family = ADRENO_5XX,
Expand Down
5 changes: 5 additions & 0 deletions drivers/gpu/drm/msm/adreno/adreno_gpu.h
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Original file line number Diff line number Diff line change
Expand Up @@ -281,6 +281,11 @@ static inline int adreno_is_a430(const struct adreno_gpu *gpu)
return adreno_is_revn(gpu, 430);
}

static inline int adreno_is_a505(const struct adreno_gpu *gpu)
{
return adreno_is_revn(gpu, 505);
}

static inline int adreno_is_a506(const struct adreno_gpu *gpu)
{
return adreno_is_revn(gpu, 506);
Expand Down

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