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RISC-V: Allow rounding mode control for RVV floating-point add
According to the doc as below, we need to support the rounding mode of the RVV floating-point, both the static and dynamice frm. riscv-non-isa/rvv-intrinsic-doc#226 For tracking and development friendly, We will take some steps to support all rounding modes for the RVV floating-point rounding modes. 1. Allow rounding mode control by one intrinsic (aka this patch), vfadd. 2. Support static rounding mode control by mode switch, like fixed-point. 3. Support dynamice round mode control by mode switch. 4. Support the rest floating-point instructions for frm. Please *NOTE* this patch only allow the rounding mode control for the vfadd intrinsic API, and the related frm will be coverred by step 2. Signed-off-by: Pan Li <pan2.li@intel.com> Co-Authored by: Juzhe-Zhong <juzhe.zhong@rivai.ai> gcc/ChangeLog: * config/riscv/riscv-protos.h (enum floating_point_rounding_mode): Add macro for static frm min and max. * config/riscv/riscv-vector-builtins-bases.cc (class binop_frm): New class for floating-point with frm. (BASE): Add vfadd for frm. * config/riscv/riscv-vector-builtins-bases.h: Likewise. * config/riscv/riscv-vector-builtins-functions.def (vfadd_frm): Likewise. * config/riscv/riscv-vector-builtins-shapes.cc (struct alu_frm_def): New struct for alu with frm. (SHAPE): Add alu with frm. * config/riscv/riscv-vector-builtins-shapes.h: Likewise. * config/riscv/riscv-vector-builtins.cc (function_checker::report_out_of_range_and_not): New function for report out of range and not val. (function_checker::require_immediate_range_or): New function for checking in range or one val. * config/riscv/riscv-vector-builtins.h: Add function decl. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-frm-error.c: New test. * gcc.target/riscv/rvv/base/float-point-frm.c: New test.
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gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-error.c
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/* { dg-do compile } */ | ||
/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ | ||
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#include "riscv_vector.h" | ||
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typedef float float32_t; | ||
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void test_float_point_frm_error (float32_t *out, vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) | ||
{ | ||
vfloat32m1_t v1 = __riscv_vfadd_vv_f32m1_rm (op1, op2, 5, vl); /* { dg-error {passing 5 to argument 3 of '__riscv_vfadd_vv_f32m1_rm', which expects a value in the range \[0, 4\] or 7} } */ | ||
vfloat32m1_t v2 = __riscv_vfadd_vv_f32m1_rm (v1, v1, 6, vl); /* { dg-error {passing 6 to argument 3 of '__riscv_vfadd_vv_f32m1_rm', which expects a value in the range \[0, 4\] or 7} } */ | ||
vfloat32m1_t v3 = __riscv_vfadd_vv_f32m1_rm (v2, v2, 8, vl); /* { dg-error {passing 8 to argument 3 of '__riscv_vfadd_vv_f32m1_rm', which expects a value in the range \[0, 4\] or 7} } */ | ||
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__riscv_vse32_v_f32m1 (out, v3, vl); | ||
} |
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/* { dg-do compile } */ | ||
/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ | ||
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#include "riscv_vector.h" | ||
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typedef float float32_t; | ||
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vfloat32m1_t | ||
test_riscv_vfadd_vv_f32m1_rm (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) { | ||
return __riscv_vfadd_vv_f32m1_rm (op1, op2, 0, vl); | ||
} | ||
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vfloat32m1_t | ||
test_vfadd_vv_f32m1_m_rm(vbool32_t mask, vfloat32m1_t op1, vfloat32m1_t op2, | ||
size_t vl) { | ||
return __riscv_vfadd_vv_f32m1_m_rm(mask, op1, op2, 0, vl); | ||
} | ||
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vfloat32m1_t | ||
test_vfadd_vf_f32m1_rm(vfloat32m1_t op1, float32_t op2, size_t vl) { | ||
return __riscv_vfadd_vf_f32m1_rm(op1, op2, 0, vl); | ||
} | ||
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vfloat32m1_t | ||
test_vfadd_vf_f32m1_m_rm(vbool32_t mask, vfloat32m1_t op1, float32_t op2, | ||
size_t vl) { | ||
return __riscv_vfadd_vf_f32m1_m_rm(mask, op1, op2, 0, vl); | ||
} | ||
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/* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 4 } } */ |