Let's dream...

hierarchy.ys

@@ -1 +1 @@
-hierarchy -top sleep
+hierarchy -top Dream

sonar-project.properties

@@ -1,4 +1,4 @@
 sonar.projectKey=github-bugfinder-sample
 sonar.projectName=GitHub - BugFinder Sample
 sonar.sources=./src
-sonar.vhdl.topLevelEntity=sleep
+sonar.vhdl.topLevelEntity=Dream

src/sleep.vhd

@@ -1,18 +1,19 @@
 library ieee;
 use ieee.std_logic_1164.all;
 
-entity sleep is
+entity Dream is
   port (
     clk : in std_logic;
     rst : in std_logic;
     i1 : in std_logic;
     i2 : in std_logic;
     o1 : out std_logic;
-    o2 : out std_logic
+    o2 : out std_logic;
+    toto : out std_logic_vector(0 to 3)
   );
 end entity;
 
-architecture rtl of sleep is
+architecture rtl of Dream is
 begin
   p1 : process (clk) is
   begin
@@ -32,7 +33,10 @@ begin
         o2 <= '0';
       else
         o2 <= i1 or i2;
+        toto(0) <= '1';
+        toto(1) <= i1 or i2;
       end if;
     end if;
   end process;
+  toto(3) <= i1 or i2;
 end architecture;