Name		Name	Last commit message	Last commit date
Latest commit History 79 Commits
.gitignore		.gitignore
ALU_16bit.bdf		ALU_16bit.bdf
ALU_16bit.bsf		ALU_16bit.bsf
ALU_16bit.v		ALU_16bit.v
ALU_16bit_t.v		ALU_16bit_t.v
ALU_16bit_v.v		ALU_16bit_v.v
ALU_4bit.bdf		ALU_4bit.bdf
ALU_4bit.bsf		ALU_4bit.bsf
ALU_4bit.v		ALU_4bit.v
ALU_4bit_v.bsf		ALU_4bit_v.bsf
ALU_4bit_v.v		ALU_4bit_v.v
Address_Selector.bsf		Address_Selector.bsf
Address_Selector.v		Address_Selector.v
All_LEDs_on_button.txt		All_LEDs_on_button.txt
CPU_Decoder00.bsf		CPU_Decoder00.bsf
CPU_Decoder00.v		CPU_Decoder00.v
CPU_Decoder01.bsf		CPU_Decoder01.bsf
CPU_Decoder01.v		CPU_Decoder01.v
CPU_Decoder10.bsf		CPU_Decoder10.bsf
CPU_Decoder10.v		CPU_Decoder10.v
CPU_Decoder11.bsf		CPU_Decoder11.bsf
CPU_Decoder11.v		CPU_Decoder11.v
CarryLookaheadAdder.bsf		CarryLookaheadAdder.bsf
CarryLookaheadAdder.v		CarryLookaheadAdder.v
ControlUnit.bdf		ControlUnit.bdf
ControlUnit.bsf		ControlUnit.bsf
ControlUnitGPIO.bdf		ControlUnitGPIO.bdf
ControlUnit_v.v		ControlUnit_v.v
ControlUnit_v_t.v		ControlUnit_v_t.v
Core.bdf		Core.bdf
Core_v.v		Core_v.v
Core_v_t.v		Core_v_t.v
EIGHTtoONE_MUX16bit.bsf		EIGHTtoONE_MUX16bit.bsf
EIGHTtoONE_MUX16bit.v		EIGHTtoONE_MUX16bit.v
FOURtoONE_MUX.bsf		FOURtoONE_MUX.bsf
FOURtoONE_MUX.v		FOURtoONE_MUX.v
GPIO_A.bdf		GPIO_A.bdf
GPIO_A.bsf		GPIO_A.bsf
GPIO_A_TEST.bdf		GPIO_A_TEST.bdf
GPIO_A_TEST_v.v		GPIO_A_TEST_v.v
GPIO_A_v.v		GPIO_A_v.v
GPIO_Board.bsf		GPIO_Board.bsf
GPIO_Board.v		GPIO_Board.v
GPIO_Board_test.v		GPIO_Board_test.v
GPIO_Single_Cell.bdf		GPIO_Single_Cell.bdf
GPIO_Single_Cell.bsf		GPIO_Single_Cell.bsf
GPIO_Single_Cell_v.v		GPIO_Single_Cell_v.v
IR.bsf		IR.bsf
IR.v		IR.v
Iterate_LEDs.txt		Iterate_LEDs.txt
LED_Blink.txt		LED_Blink.txt
LED_Write_rom.txt		LED_Write_rom.txt
LED_on_keystroke.txt		LED_on_keystroke.txt
PC.bsf		PC.bsf
PC.v		PC.v
PS2.bdf		PS2.bdf
PS2.bsf		PS2.bsf
PS2.sof		PS2.sof
PS2_master.bsf		PS2_master.bsf
PS2_v.v		PS2_v.v
Processor.cdf		Processor.cdf
Processor.qpf		Processor.qpf
Processor.sof		Processor.sof
Processor_Doc.pdf		Processor_Doc.pdf
RAM1.bsf		RAM1.bsf
RAM1.qip		RAM1.qip
RAM1.v		RAM1.v
RAM1_bb.v		RAM1_bb.v
RAM2.qip		RAM2.qip
RAM2.v		RAM2.v
RAM2_bb.v		RAM2_bb.v
README.md		README.md
RegisterFile.bdf		RegisterFile.bdf
RegisterFile.bsf		RegisterFile.bsf
RegisterFile_v.v		RegisterFile_v.v
THREEtoEIGHT_decoder.bsf		THREEtoEIGHT_decoder.bsf
THREEtoEIGHT_decoder.v		THREEtoEIGHT_decoder.v
TWOtoONE_MUX.bsf		TWOtoONE_MUX.bsf
TWOtoONE_MUX.v		TWOtoONE_MUX.v
Top_Level.bdf		Top_Level.bdf
Top_Level_ModelSim.bdf		Top_Level_ModelSim.bdf
Top_Level_ModelSim_v.v		Top_Level_ModelSim_v.v
Top_Level_ModelSim_v_t.v		Top_Level_ModelSim_v_t.v
Two_to_Four_MUX45bit.bsf		Two_to_Four_MUX45bit.bsf
Two_to_Four_MUX45bit.v		Two_to_Four_MUX45bit.v
Two_to_Four_MUX46bit.bsf		Two_to_Four_MUX46bit.bsf
VGA.bdf		VGA.bdf
VGA.bsf		VGA.bsf
VGA_TEST.bdf		VGA_TEST.bdf
Write_keystroke_to LED.txt		Write_keystroke_to LED.txt
altera_mf.v		altera_mf.v
and5_1.bsf		and5_1.bsf
and5_1.v		and5_1.v
clock_div.bsf		clock_div.bsf
clock_div.v		clock_div.v
decoder.bsf		decoder.bsf
decoder.v		decoder.v
decoder2to4.bsf		decoder2to4.bsf
decoder2to4.v		decoder2to4.v
fifo.v		fifo.v

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Comp-Arch-Processor

This is the project for Rowan University's Computer Architecture class, ECE 09243 Section 3 Team l under the Direction of Professor Michael Muhlbaier.

Our project is a Harvard architecture processor with tristate data buses. See full documentation here.

Team Members:
Lonnie L. Souder II
Jacob Epifano (https://github.com/jrepifano)
Sean McGuire (https://github.com/mcguires5)
Ardit Pranvoku
Ryan Drexel

Llcoolsouder/Comp-Arch-Processor

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