Add two types of debug facilities

1. allow to trigger debug interrupt from dmi register
2. pass trace info to top to enable ILA based tracing

.gitignore

@@ -10,3 +10,14 @@ ControlPlanes.v
 src/main/scala/.idea/
 src/main/scala/build.sbt
 src/main/scala/project/
+
+.idea/
+boom-ether.err
+bootrom/bootrom.txt
+emulator/boom-failed.md
+emulator/log.txt
+emulator/serial6*
+fpga/.Xil/
+fpga/bbl.elf.txt
+fpga/vivado_*.str
+fpga/vmlinux.txt

fpga/Makefile.sw

@@ -5,6 +5,10 @@ endif
 
 build_dir = $(realpath ./build)
 SW_PATH = $(abspath ../../sw)
+# SW_PATH = $(HOME)/build-dir/boom-sw
+
+
+config_prefix ?= notset
 
 $(SW_PATH):
 	@echo "Do you want to put all software repos under $(SW_PATH) (You can modify 'SW_PATH' in Makefile.sw)? [y/n]"
@@ -31,7 +35,7 @@ BBL_REPO_PATH = $(SW_PATH)/riscv-pk
 # BBL_BUILD_COMMIT = f0295b7f7ca1b301a248fb1e7e332be70983e2dc
 
 # BOOM
-BBL_BUILD_COMMIT = e4230fe249c91bd917899c483184afe19158b3f4
+BBL_BUILD_COMMIT = 8cab179810e71c4361d30631da9bc3967522828f
 
 BBL_BUILD_PATH = $(BBL_REPO_PATH)/build
 BBL_ELF_BUILD = $(BBL_BUILD_PATH)/bbl
@@ -41,7 +45,9 @@ BBL_PAYLOAD = $(LINUX_ELF)
 # autoMBA:
 # BBL_CONFIG = --host=riscv64-unknown-elf --with-payload=$(BBL_PAYLOAD) --with-arch=rv64imac --enable-logo
 # BOOM:
-BBL_CONFIG = --host=riscv64-unknown-elf --with-payload=$(BBL_PAYLOAD) --with-arch=rv64imafd --enable-logo
+# BBL_CONFIG = --host=riscv64-unknown-elf --with-payload=$(BBL_PAYLOAD) --with-arch=rv64imafd --enable-logo
+# Both:
+BBL_CONFIG = --host=riscv64-unknown-elf --with-payload=$(BBL_PAYLOAD) --with-arch=rv64ima --enable-logo
 
 BBL_ELF = $(build_dir)/bbl.elf
 BBL_BIN = $(build_dir)/linux.bin
@@ -56,7 +62,7 @@ LINUX_REPO_PATH = $(SW_PATH)/riscv-linux
 # LINUX_BUILD_COMMIT = a57318a489074cf5768e97de2b45eac47e474731
 
 # BOOM:
-LINUX_BUILD_COMMIT = 6704f026851c9f2f0484cc87cb7867b54ff42e3b
+LINUX_BUILD_COMMIT = adc341d40a7fc4f6c9e4139d7c451b1068576556
 
 LINUX_ELF_BUILD = $(LINUX_REPO_PATH)/vmlinux
 LINUX_ELF = $(build_dir)/vmlinux
@@ -77,7 +83,7 @@ $(BBL_ELF): $(BBL_ELF_BUILD)
 
 $(BBL_REPO_PATH): | $(SW_PATH)
 	mkdir -p $@
-	git clone git@10.30.16.1:pard/riscv_bbl.git $@
+	git clone https://github.com/shinezyy/riscv-pk.git $@
 
 $(BBL_BUILD_PATH): $(BBL_PAYLOAD) | $(BBL_REPO_PATH)
 	mkdir -p $@
@@ -106,7 +112,7 @@ $(LINUX_REPO_PATH): | $(SW_PATH)
 	mkdir -p $@
 	@/bin/echo -e "\033[1;31mBy default, a shallow clone with only 1 commit history is performed, since the commit history is very large.\nThis is enough for building the project.\nTo fetch full history, run 'git fetch --unshallow' under $(LINUX_REPO_PATH).\033[0m"
 	git clone --depth 1 https://github.com/shinezyy/riscv-linux.git $@
-	cd $@ && make ARCH=riscv emu_boomconfig
+	cd $@ && make ARCH=riscv $(config_prefix)boom_config
 
 $(ROOTFS_PATH): | $(SW_PATH)
 	mkdir -p $@
@@ -122,7 +128,7 @@ $(LINUX_ELF_BUILD): | $(LINUX_REPO_PATH) $(ROOTFS_PATH)
 	$(MAKE) -C $(ROOTFS_PATH)
 	cd $(@D) && \
 		git checkout $(LINUX_BUILD_COMMIT) && \
-		(($(MAKE) CROSS_COMPILE=$(RISCV_PREFIX) ARCH=riscv fpgaboom_defconfig ) && \
+		(($(MAKE) CROSS_COMPILE=$(RISCV_PREFIX) ARCH=riscv $(config_prefix)boom_defconfig ) && \
 		($(MAKE) CROSS_COMPILE=$(RISCV_PREFIX) ARCH=riscv vmlinux ) \
 		|| (git checkout @{-1}; false)) && \
 		git checkout @{-1}

src/main/scala/debug/DebugBundles.scala

@@ -0,0 +1,18 @@
+
+package freechips.rocketchip.debug
+
+import chisel3._
+import chisel3.util._
+import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.tile.{CoreBundle, HasCoreParameters}
+
+
+class DebugCSRIntIO extends Bundle() {
+  // from CSR/core's perspective
+  val dmiInterrupt = Input(Bool())
+  val ndmiInterrupts = Output(UInt(16.W))
+  val eipOutstanding = Output(Bool())
+  val csrOutInt = Output(Bool())
+  val reg_mip = Output(UInt(64.W))
+}
+

src/main/scala/devices/debug/Debug.scala

@@ -3,8 +3,10 @@
 package freechips.rocketchip.devices.debug
 
 import Chisel._
-import chisel3.core.WireInit
+import boom.common._
+import chisel3.core.{VecInit, WireInit}
 import freechips.rocketchip.config._
+import freechips.rocketchip.debug.DebugCSRIntIO
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.regmapper._
 import freechips.rocketchip.rocket.Instructions
@@ -13,8 +15,10 @@ import freechips.rocketchip.interrupts._
 import freechips.rocketchip.util._
 import freechips.rocketchip.util.property._
 import freechips.rocketchip.devices.debug.systembusaccess._
-import freechips.rocketchip.subsystem.NL2CacheWays
+import freechips.rocketchip.subsystem.{NL2CacheWays, NTiles}
+import freechips.rocketchip.system.UseEmu
 import freechips.rocketchip.tile.XLen
+import ila.BoomCSRILABundle
 import lvna.{ControlPlaneIO, HasControlPlaneParameters}
 
 object DsbBusConsts {
@@ -411,6 +415,7 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int, beatBytes: I
       val innerCtrl = (new DecoupledIO(new DebugInternalBundle())).flip
       val debugUnavail = Vec(nComponents, Bool()).asInput
       val cp = new ControlPlaneIO().flip()
+      val zid = Vec(p(NTiles), new DebugCSRIntIO().flip())
     })
 
 
@@ -502,7 +507,7 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int, beatBytes: I
         haveResetBitRegs(io.innerCtrl.bits.hartsel) := false.B
       }
     }
- 
+
     DMSTATUSRdData.allresumeack := ~resumeReqRegs(selectedHartReg) && ~resumereq
     DMSTATUSRdData.anyresumeack := ~resumeReqRegs(selectedHartReg) && ~resumereq
 
@@ -686,6 +691,41 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int, beatBytes: I
       }
     }
 
+    val periodic_debug_int = WireInit(false.B)
+
+    val ocd_debut_int = WireInit(false.B)
+
+    val debug_interrupt_en = ocd_debut_int | periodic_debug_int
+
+    when (debug_interrupt_en) {
+      dprintf(DEBUG_ETHER, "debug enabled!\n")
+    }
+
+    //counter
+    val debug_int_counter_local = Counter(debug_interrupt_en, 1<<16)
+
+    if (p(UseEmu) && DEBUG_ETHER) {
+      val ztimer = GTimer()
+
+//      val start = 0.U
+      val start = 34603008.U
+      val period_small = ((1 << 20) - 1).U
+
+      when ((ztimer & period_small) === 0.U) {
+        dprintf(DEBUG_ETHER, "small periodic timer triggered @ %d!\n", ztimer)
+        when (ztimer >= start) {
+          periodic_debug_int := true.B
+          dprintf(DEBUG_ETHER, "local counter = %d, remote counter = %d\n",
+            debug_int_counter_local._1, io.zid(io.cp.hartSel).ndmiInterrupts)
+        }
+      }
+    }
+
+    // send to core
+    io.zid.zipWithIndex.foreach { case (zidio, i) =>
+      zidio.dmiInterrupt := debug_interrupt_en && io.cp.hartSel === i.U
+    }
+
     val (sbcsFields, sbAddrFields, sbDataFields):
     (Seq[RegField], Seq[Seq[RegField]], Seq[Seq[RegField]]) = sb2tlOpt.map{ sb2tl =>
       SystemBusAccessModule(sb2tl,io.dmactive)(p)
@@ -757,6 +797,13 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int, beatBytes: I
       (CORE_PC_READ_DONE    << 2) -> Seq(RWNotify(1,      0.U,                      io.cp.updateData, WireInit(false.B), io.cp.doneReadPC,      None)),
       (CORE_PC_READ         << 2) -> Seq(RWNotify(1,      0.U,                      io.cp.updateData, WireInit(false.B), io.cp.readPC,      None)),
 
+      (CORE_INT_DEBUG       << 2) -> Seq(RWNotify(1,      0.U,                      io.cp.updateData, WireInit(false.B), ocd_debut_int,   None)),
+      (CORE_N_INT_DEBUG     << 2) -> Seq(RegField.r(16,   io.zid(io.cp.hartSel).ndmiInterrupts,   RegFieldDesc("num-debug-interrupts", "times that debug interrrupt has being triggered"))),
+      (CORE_N_INT_DEBUG_LOCAL     << 2) -> Seq(RegField.r(16,   debug_int_counter_local._1,   RegFieldDesc("num-debug-interrupts-local", "times that debug interrrupt has being triggered"))),
+      (CORE_CSR_INT_VALID       << 2) -> Seq(RegField.r(1,   io.zid(io.cp.hartSel).csrOutInt,   RegFieldDesc("eipOutstanding", "eipOutstanding"))),
+
+      (CORE_CSR_PENDING_INT_HI     << 2) -> Seq(RegField.r(32,   io.zid(io.cp.hartSel).reg_mip(63, 32),   RegFieldDesc("1", "1"))),
+      (CORE_CSR_PENDING_INT_LO     << 2) -> Seq(RegField.r(32,   io.zid(io.cp.hartSel).reg_mip(31, 0),   RegFieldDesc("1", "1"))),
 
       (CP_DSID_SEL    << 2) -> Seq(RWNotify(dsidWidth,       io.cp.dsidSel,         io.cp.updateData, WireInit(false.B), io.cp.dsidSelWen,   None))
     )
@@ -767,6 +814,7 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int, beatBytes: I
         x := abstractDataNxt(i)
       }
     }
+
     // ... and also by custom register read (if implemented)
     val (customs, customParams) = customNode.in.unzip
     val needCustom = (customs.size > 0) && (customParams.head.addrs.size > 0)
@@ -1116,12 +1164,17 @@ class TLDebugModuleInnerAsync(device: Device, getNComponents: () => Int, beatByt
       val debugUnavail    = Vec(getNComponents(), Bool()).asInput
       val psd = new PSDTestMode().asInput
       val cp = new ControlPlaneIO().flip()
+      val zid = Vec(p(NTiles), new DebugCSRIntIO().flip())
     })
 
     dmInner.module.io.cp <> io.cp
     dmInner.module.io.innerCtrl := FromAsyncBundle(io.innerCtrl)
     dmInner.module.io.dmactive := ~ResetCatchAndSync(clock, ~io.dmactive, "dmactiveSync", io.psd)
     dmInner.module.io.debugUnavail := io.debugUnavail
+
+    dmInner.module.io.zid <> io.zid
+
+//    dprintf(DEBUG_ETHER, dmInner.module.io.zid(0).dmiInterrupt, "DMI int for core 0 triggered\n")
   }
 }
 
@@ -1152,6 +1205,7 @@ class TLDebugModule(beatBytes: Int)(implicit p: Parameters) extends LazyModule {
       val dmi = new ClockedDMIIO().flip
       val psd = new PSDTestMode().asInput
       val cp = new ControlPlaneIO().flip()
+      val zid = Vec(p(NTiles), new DebugCSRIntIO().flip())
     })
 
     dmInner.module.io.cp <> io.cp
@@ -1167,5 +1221,7 @@ class TLDebugModule(beatBytes: Int)(implicit p: Parameters) extends LazyModule {
 
     io.ctrl <> dmOuter.module.io.ctrl
 
+    dmInner.module.io.zid <> io.zid
+//    dprintf(DEBUG_ETHER, dmInner.module.io.zid(0).dmiInterrupt, "DMI int for core 0 triggered\n")
   }
 }

src/main/scala/devices/debug/dm_registers.scala

@@ -373,6 +373,19 @@ object DMI_RegAddrs {
   def CORE_PC_READ_DONE  = 0x73
 
   def CORE_PC_READ  = 0x74
+
+  def CORE_INT_DEBUG = 0x75
+
+  def CORE_N_INT_DEBUG = 0x76
+
+  def CORE_N_INT_DEBUG_LOCAL = 0x77
+
+  def CORE_CSR_INT_VALID = 0x78
+
+  def CORE_CSR_PENDING_INT_LO = 0x79
+
+  def CORE_CSR_PENDING_INT_HI = 0x7a
+
 }
 
 class DMSTATUSFields extends Bundle {

src/main/scala/lvna/ILA.scala

@@ -1,6 +1,6 @@
 // See LICENSE.SiFive for license details.
 
-package util
+package ila
 
 import Chisel._
 
@@ -21,3 +21,33 @@ class ILABundle extends Bundle {
   val rt_raddr = UInt(OUTPUT, 5)
   val rt_rdata = UInt(OUTPUT, 64)
 }
+
+class BoomCSRILABundle extends Bundle {
+  val trigger = Bool(OUTPUT)
+  val reg_mip = UInt(OUTPUT, 64)
+  val csr_rw_cmd = UInt(OUTPUT, 3)
+  val csr_rw_wdata = UInt(OUTPUT, 64)
+  val wr_mip = Bool(OUTPUT)
+  val reg_mbadaddr = UInt(OUTPUT, 64)
+}
+
+class FPGATraceBaseBundle(val commWidth: Int) extends Bundle {
+  val traces = Vec(commWidth, new Bundle {
+    val valid = Bool()
+    val commPriv = UInt(OUTPUT, 2)
+    val commPC = UInt(OUTPUT, 40)
+    val commInst = UInt(OUTPUT, 32)
+
+    val isFloat = Bool()
+    val wbValueValid = Bool()
+    val wbARFN = UInt(OUTPUT, 6)
+    val wbValue = UInt(OUTPUT, 64)
+
+  })
+}
+
+class FPGATraceExtraBundle extends Bundle { // For rocket's delayed wb
+  val delayedWbValid = Bool()
+  val wbARFN = UInt(OUTPUT, 6)
+  val wbValue = UInt(OUTPUT, 64)
+}

src/main/scala/lvna/controlplane/ControlPlane.scala

@@ -76,6 +76,8 @@ class ControlPlaneIO(implicit val p: Parameters) extends Bundle with HasControlP
   val autoPCSnapShotWen   = Bool(INPUT)
   val autoPCSnapShotEn    = Bool(OUTPUT)
   val PC                  = UInt(OUTPUT, p(XLen))
+
+  val assertDebugInt      = Bool(INPUT)
 }
 
 /* From ControlPlane's View */
@@ -249,9 +251,7 @@ with HasTokenBucketParameters
     when (GTimer() >= cycleCounter) {
       for (i <- 0 until nTiles) {
         // 输出每段时间内，产生了多少流量，用于精细观察流量控制策略
-        // printf("Traffic time: %d dsid: %d traffic: %d\n", cycleCounter, i.U, io.traffics(i) - lastTraffic(i))
         // 输出到了每个时间点后的CDF，用于看整体的流量曲线，观察流量控制效果
-        printf("Traffic time: %d dsid: %d traffic: %d\n", cycleCounter, i.U, bucketState(i).traffic)
         lastTraffic(i) := bucketState(i).traffic
       }
       cycleCounter := cycleCounter + accountingCycle.U
@@ -325,9 +325,6 @@ with HasTokenBucketParameters
 
         val bandwidthUsage = ((bucketState(highPriorIndex).traffic - startTraffic) << 3).asUInt()
         startTraffic := bucketState(highPriorIndex).traffic
-        printf("limit level: %d;quota: %d/%d; traffic: %d\n", curLevel, quota, totalBW.U, bandwidthUsage)
-        printf("freq 0: %d; freq 1: %d\n", bucketParams(0).freq, bucketParams(1).freq)
-        printf("inc 0: %d; inc 1: %d\n", bucketParams(0).inc , bucketParams(1).inc)
 
         val nextLevel = Wire(UInt(4.W))
         val nextQuota = Wire(UInt(8.W))
@@ -353,7 +350,6 @@ with HasTokenBucketParameters
         curLevel := nextLevel
         quota := nextQuota
 
-        printf("next level: %d;next quota: %d\n", nextLevel, nextQuota)
       }
       when (windowCounter < windowSize.U) {
         windowCounter := windowCounter + 1.U