Fix syntax error in RTL moving default parameters to the top of the m…

…odule intercon_wb
M0stafaRady · May 28, 2023 · c7f525a · c7f525a
1 parent 7344f67
commit c7f525a
Showing 1 changed file with 16 additions and 16 deletions.
diff --git a/verilog/rtl/intercon_wb.v b/verilog/rtl/intercon_wb.v
@@ -18,20 +18,7 @@
 module intercon_wb #(
     parameter DW = 32,     // Data width
     parameter AW = 32,     // Address width
-    parameter NI = 6       // Number of interfaces
-) (
-    // Master
-    input [AW-1:0] wbm_adr_i,
-    input wbm_stb_i,
-
-    output reg [DW-1:0] wbm_dat_o,
-    output wbm_ack_o,
-
-    // Interfaces
-    input [NI*DW-1:0] wbs_dat_i,
-    input [NI-1:0] wbs_ack_i,
-    output [NI-1:0] wbs_stb_o
-);
+    parameter NI = 6,      // Number of interfaces
     parameter [NI*AW-1:0] ADR_MASK = {      // Page & Sub-page bits
         {8'hFF, {24{1'b0}} },
         {8'hFF, {24{1'b0}} },
@@ -40,7 +27,7 @@ module intercon_wb #(
         {8'hFF, {24{1'b0}} },
         {8'hFF, {24{1'b0}} }
 
-    };
+    },
     parameter [NI*AW-1:0] IFACE_ADR = {
         { 32'h2800_0000 },    // Flash Configuration Register
         { 32'h2200_0000 },    // System Control
@@ -49,7 +36,20 @@ module intercon_wb #(
         { 32'h1000_0000 },    // Flash 
         { 32'h0000_0000 }     // RAM
 
-    };
+    }
+) (
+    // Master
+    input [AW-1:0] wbm_adr_i,
+    input wbm_stb_i,
+
+    output reg [DW-1:0] wbm_dat_o,
+    output wbm_ack_o,
+
+    // Interfaces
+    input [NI*DW-1:0] wbs_dat_i,
+    input [NI-1:0] wbs_ack_i,
+    output [NI-1:0] wbs_stb_o
+);
 
     wire [NI-1: 0] iface_sel;