Add MIPS-style TLB to functional simulation

[pavelkryukov]

MIPS ISA defines that TLB miss is handled by OS.

TLB miss should generate an exception, which is handled by OS exception handler, which manipulates TLB using TLB-manipulating instructions (tlbp, tlbr, tlbwi, tlbwr)

The steps are:

1. Add TLB structure to functional simulator
2. Implement TLB-manipulation instructions
3. Add the simplest handler of TLB miss exception to MARS-like kernel (i.e. physical address = virtual address + 0x10000).