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Add ctor of MIPS instruction from string #589

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pavelkryukov opened this issue Sep 29, 2018 · 4 comments
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Add ctor of MIPS instruction from string #589

pavelkryukov opened this issue Sep 29, 2018 · 4 comments
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@pukhovv
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1 Usually one-liner tasks, but may require some deep into infrastructure. code Enhances infrastructure or refines, Requires almost no knowledge in CPU microarchitecture. good first issue Good task to start with MIPT-MIPS development S1 — ISA To solve the issue, you need knowledge about MIPS or RISC-V ISA

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@pavelkryukov
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pavelkryukov commented Sep 29, 2018 •
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Currently the only way to construct a MIPS instruction object is to decode it from 4 bytes. That's not convinient for tests (see #530), so the idea is to add a new constructor from stringed opcode:

MIPSInstr<MIPS32> instr( "sllv"); // Creates a SLLV instruction
@pavelkryukov pavelkryukov added code Enhances infrastructure or refines, Requires almost no knowledge in CPU microarchitecture. 1 Usually one-liner tasks, but may require some deep into infrastructure. S1 — ISA To solve the issue, you need knowledge about MIPS or RISC-V ISA good first issue Good task to start with MIPT-MIPS development labels Sep 29, 2018
@pavelkryukov pavelkryukov mentioned this issue Sep 29, 2018
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agrachiv commented Oct 2, 2018

What should I do in order to take this issue?

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I granted you write access to repository, and now you can put yourself as 'assignee' for that issue.
Please read our contribution.md to see our basic rules.

@pukhovv pukhovv self-assigned this Oct 3, 2018
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@pooh64 Do you have any progress in these two weeks?

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pukhovv commented Oct 18, 2018

@pavelkryukov Now I'm exploring the structure of repository and c++ literature. I plan to finish this issue within a week.

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1 Usually one-liner tasks, but may require some deep into infrastructure. code Enhances infrastructure or refines, Requires almost no knowledge in CPU microarchitecture. good first issue Good task to start with MIPT-MIPS development S1 — ISA To solve the issue, you need knowledge about MIPS or RISC-V ISA
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