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kernel/patches: update veyron clock selection logic for newer kernels
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@Maccraft123
Maccraft123 committed Jun 24, 2022
1 parent 1f605a0 commit 6662e0b
Showing 1 changed file with 84 additions and 67 deletions.
151 changes: 84 additions & 67 deletions kernel/patches/veyron.better_clock_selection_logic_and_dts_rate_list.patch
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Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
From ec207e1e1114fb922080c28e92f466d396bfe2be Mon Sep 17 00:00:00 2001
From invalid-sha-id-22080c28e92f466d396bfe2be Mon Sep 17 00:00:00 2001
From: Urja Rannikko <urjaman@gmail.com>
Date: Wed, 22 Aug 2018 18:36:40 +0000
Subject: [PATCH] drm: dw_hdmi-rockchip: better clock selection logic and
Expand All @@ -25,26 +25,33 @@ CHROMIUM: drm: rockchip/dw_hdmi-rockchip: Set cur_ctr to 0 always
CHROMIUM: drm: rockchip/dw_hdmi-rockchip: Decrease slop

Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Signed-off-by: Maya Matuszczyk <maccraft123mc@gmail.com>

---
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 272 +++++++++++++-------
1 file changed, 175 insertions(+), 97 deletions(-)
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 271 +++++++++++++-------
1 file changed, 174 insertions(+), 97 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
index 830bdd5e9b7ce..4fffaebf935f9 100644
index c14f88893868..cb7a302497a5 100644
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
@@ -73,122 +73,141 @@ struct rockchip_hdmi {
struct clk *grf_clk;
struct dw_hdmi *hdmi;
@@ -80,8 +80,13 @@ struct rockchip_hdmi {
struct regulator *avdd_0v9;
struct regulator *avdd_1v8;
struct phy *phy;
+ u32* rates;
+ u32 rates_cnt;
};

+#define CLK_SLOP(clk) ((clk) / 1000)
+#define CLK_PLUS_SLOP(clk) ((clk) + CLK_SLOP(clk))
+#define CLK_SLOP(clk) ((clk) / 1000)
+#define CLK_PLUS_SLOP(clk) ((clk) + CLK_SLOP(clk))
+
#define to_rockchip_hdmi(x) container_of(x, struct rockchip_hdmi, x)
static struct rockchip_hdmi *to_rockchip_hdmi(struct drm_encoder *encoder)
{
struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
@@ -89,118 +94,132 @@ static struct rockchip_hdmi *to_rockchip_hdmi(struct drm_encoder *encoder)
return container_of(rkencoder, struct rockchip_hdmi, encoder);
}

+/* These were the rates allowed by the driver before rates list in device tree,
+ * so keep them around as a fallback */
Expand Down Expand Up @@ -73,22 +80,16 @@ index 830bdd5e9b7ce..4fffaebf935f9 100644
+ { 0x00b3, 0x0000 },
+ { 0x2153, 0x0000 },
+ { 0x40f3, 0x0000 },
+ },
+ }, {
+ 36800000, {
+ { 0x00b3, 0x0000 },
+ { 0x2153, 0x0000 },
+ { 0x40a2, 0x0001 },
},
- }, {
- 36000000, {
- { 0x00b3, 0x0000},
- { 0x2153, 0x0000},
- { 0x40f3, 0x0000}
+ }, {
+ 46000000, {
+ 36800000, {
+ { 0x00b3, 0x0000 },
+ { 0x2142, 0x0001 },
+ { 0x2153, 0x0000 },
+ { 0x40a2, 0x0001 },
},
- }, {
Expand All @@ -97,8 +98,8 @@ index 830bdd5e9b7ce..4fffaebf935f9 100644
- { 0x2153, 0x0000},
- { 0x40f3, 0x0000}
+ }, {
+ 61333000, {
+ { 0x0072, 0x0001 },
+ 46000000, {
+ { 0x00b3, 0x0000 },
+ { 0x2142, 0x0001 },
+ { 0x40a2, 0x0001 },
},
Expand All @@ -108,20 +109,20 @@ index 830bdd5e9b7ce..4fffaebf935f9 100644
- { 0x2142, 0x0001},
- { 0x40a2, 0x0001},
+ }, {
+ 73600000, {
+ 61333000, {
+ { 0x0072, 0x0001 },
+ { 0x2142, 0x0001 },
+ { 0x4061, 0x0002 },
+ { 0x40a2, 0x0001 },
},
- }, {
- 65000000, {
- { 0x0072, 0x0001},
- { 0x2142, 0x0001},
- { 0x40a2, 0x0001},
+ }, {
+ 92000000, {
+ 73600000, {
+ { 0x0072, 0x0001 },
+ { 0x2145, 0x0002 },
+ { 0x2142, 0x0001 },
+ { 0x4061, 0x0002 },
},
- }, {
Expand All @@ -130,8 +131,8 @@ index 830bdd5e9b7ce..4fffaebf935f9 100644
- { 0x217e, 0x0002},
- { 0x4061, 0x0002}
+ }, {
+ 122666000, {
+ { 0x0051, 0x0002 },
+ 92000000, {
+ { 0x0072, 0x0001 },
+ { 0x2145, 0x0002 },
+ { 0x4061, 0x0002 },
},
Expand All @@ -141,18 +142,18 @@ index 830bdd5e9b7ce..4fffaebf935f9 100644
- { 0x2145, 0x0002},
- { 0x4061, 0x0002}
+ }, {
+ 147200000, {
+ 122666000, {
+ { 0x0051, 0x0002 },
+ { 0x2145, 0x0002 },
+ { 0x4064, 0x0003 },
+ { 0x4061, 0x0002 },
},
- }, {
- 83500000, {
- { 0x0072, 0x0001},
+ }, {
+ 184000000, {
+ 147200000, {
+ { 0x0051, 0x0002 },
+ { 0x214c, 0x0003 },
+ { 0x2145, 0x0002 },
+ { 0x4064, 0x0003 },
},
- }, {
Expand All @@ -161,8 +162,8 @@ index 830bdd5e9b7ce..4fffaebf935f9 100644
- { 0x2145, 0x0002},
- { 0x4061, 0x0002}
+ }, {
+ 226666000, {
+ { 0x0040, 0x0003 },
+ 184000000, {
+ { 0x0051, 0x0002 },
+ { 0x214c, 0x0003 },
+ { 0x4064, 0x0003 },
},
Expand All @@ -172,20 +173,20 @@ index 830bdd5e9b7ce..4fffaebf935f9 100644
- { 0x2145, 0x0002},
- { 0x4061, 0x0002}
+ }, {
+ 272000000, {
+ 226666000, {
+ { 0x0040, 0x0003 },
+ { 0x214c, 0x0003 },
+ { 0x5a64, 0x0003 },
+ { 0x4064, 0x0003 },
},
- }, {
- 146250000, {
- { 0x0051, 0x0002},
- { 0x2145, 0x0002},
- { 0x4061, 0x0002}
+ }, {
+ 340000000, {
+ 272000000, {
+ { 0x0040, 0x0003 },
+ { 0x3b4c, 0x0003 },
+ { 0x214c, 0x0003 },
+ { 0x5a64, 0x0003 },
},
- }, {
Expand All @@ -194,12 +195,18 @@ index 830bdd5e9b7ce..4fffaebf935f9 100644
- { 0x214c, 0x0003},
- { 0x4064, 0x0003}
+ }, {
+ 600000000, {
+ { 0x1a40, 0x0003 },
+ 340000000, {
+ { 0x0040, 0x0003 },
+ { 0x3b4c, 0x0003 },
+ { 0x5a64, 0x0003 },
},
- }, {
+ }, {
+ 600000000, {
+ { 0x1a40, 0x0003 },
+ { 0x3b4c, 0x0003 },
+ { 0x5a64, 0x0003 },
+ },
+ }, {
~0UL, {
- { 0x00a0, 0x000a },
Expand All @@ -214,7 +221,7 @@ index 830bdd5e9b7ce..4fffaebf935f9 100644

static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = {
- /* pixelclk bpp8 bpp10 bpp12 */
+ /* pixelclk bpp8 bpp10 bpp12 */
+ /* pixelclk bpp8 bpp10 bpp12 */
{
- 40000000, { 0x0018, 0x0018, 0x0018 },
- }, {
Expand All @@ -227,27 +234,26 @@ index 830bdd5e9b7ce..4fffaebf935f9 100644
- 83500000, { 0x0028, 0x0038, 0x0038 },
- }, {
- 146250000, { 0x0038, 0x0038, 0x0038 },
- }, {
+ 600000000, { 0x0000, 0x0000, 0x0000 },
}, {
- 148500000, { 0x0000, 0x0038, 0x0038 },
- }, {
- ~0UL, { 0x0000, 0x0000, 0x0000},
- }
+ 600000000, { 0x0000, 0x0000, 0x0000 },
+ }, {
+ ~0UL, { 0x0000, 0x0000, 0x0000 },
+ },
+ ~0UL, { 0x0000, 0x0000, 0x0000},
}
};

static const struct dw_hdmi_phy_config rockchip_phy_config[] = {
/*pixelclk symbol term vlev*/
- /*pixelclk symbol term vlev*/
- { 74250000, 0x8009, 0x0004, 0x0272},
- { 148500000, 0x802b, 0x0004, 0x028d},
- { 297000000, 0x8039, 0x0005, 0x028d},
- { ~0UL, 0x0000, 0x0000, 0x0000}
+ /*pixelclk symbol term vlev*/
+ { CLK_PLUS_SLOP(74250000), 0x8009, 0x0004, 0x0272},
+ { CLK_PLUS_SLOP(165000000), 0x802b, 0x0004, 0x0209},
+ { CLK_PLUS_SLOP(297000000), 0x8039, 0x0005, 0x028d},
+ { ~0UL, 0x0000, 0x0000, 0x0000}
+ { ~0UL, 0x0000, 0x0000, 0x0000}
};

static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
Expand All @@ -257,9 +263,9 @@ index 830bdd5e9b7ce..4fffaebf935f9 100644

hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
if (IS_ERR(hdmi->regmap)) {
@@ -216,27 +235,55 @@ static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
return PTR_ERR(hdmi->grf_clk);
}
@@ -237,27 +256,55 @@ static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
if (IS_ERR(hdmi->avdd_1v8))
return PTR_ERR(hdmi->avdd_1v8);

+ if ((rates_cnt = of_property_count_u32_elems(np, "rockchip,hdmi-rates-hz")) > 0) {
+ int rv;
Expand Down Expand Up @@ -323,7 +329,7 @@ index 830bdd5e9b7ce..4fffaebf935f9 100644
}

static void dw_hdmi_rockchip_encoder_disable(struct drm_encoder *encoder)
@@ -248,7 +295,39 @@ dw_hdmi_rockchip_encoder_mode_fixup(struct drm_encoder *encoder,
@@ -269,7 +316,39 @@ dw_hdmi_rockchip_encoder_mode_fixup(struct drm_encoder *encoder,
const struct drm_display_mode *mode,
struct drm_display_mode *adj_mode)
{
Expand Down Expand Up @@ -364,59 +370,70 @@ index 830bdd5e9b7ce..4fffaebf935f9 100644
}

static void dw_hdmi_rockchip_encoder_mode_set(struct drm_encoder *encoder,
@@ -304,6 +383,7 @@ dw_hdmi_rockchip_encoder_atomic_check(struct drm_encoder *encoder,
@@ -325,6 +404,7 @@ dw_hdmi_rockchip_encoder_atomic_check(struct drm_encoder *encoder,
}

static const struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_funcs = {
+ .mode_valid = dw_hdmi_rockchip_encoder_mode_valid,
.mode_fixup = dw_hdmi_rockchip_encoder_mode_fixup,
.mode_set = dw_hdmi_rockchip_encoder_mode_set,
.enable = dw_hdmi_rockchip_encoder_enable,
@@ -404,7 +484,6 @@ static struct rockchip_hdmi_chip_data rk3228_chip_data = {
@@ -425,7 +505,6 @@ static struct rockchip_hdmi_chip_data rk3228_chip_data = {
};

static const struct dw_hdmi_plat_data rk3228_hdmi_drv_data = {
- .mode_valid = dw_hdmi_rockchip_mode_valid,
.mpll_cfg = rockchip_mpll_cfg,
.cur_ctr = rockchip_cur_ctr,
.phy_config = rockchip_phy_config,
@@ -421,7 +500,6 @@ static struct rockchip_hdmi_chip_data rk3288_chip_data = {
@@ -442,7 +521,6 @@ static struct rockchip_hdmi_chip_data rk3288_chip_data = {
};

static const struct dw_hdmi_plat_data rk3288_hdmi_drv_data = {
- .mode_valid = dw_hdmi_rockchip_mode_valid,
.mpll_cfg = rockchip_mpll_cfg,
.cur_ctr = rockchip_cur_ctr,
.phy_config = rockchip_phy_config,
@@ -441,7 +519,6 @@ static struct rockchip_hdmi_chip_data rk3328_chip_data = {
@@ -462,7 +540,6 @@ static struct rockchip_hdmi_chip_data rk3328_chip_data = {
};

static const struct dw_hdmi_plat_data rk3328_hdmi_drv_data = {
- .mode_valid = dw_hdmi_rockchip_mode_valid,
.mpll_cfg = rockchip_mpll_cfg,
.cur_ctr = rockchip_cur_ctr,
.phy_config = rockchip_phy_config,
@@ -459,7 +536,6 @@ static struct rockchip_hdmi_chip_data rk3399_chip_data = {
@@ -480,7 +557,6 @@ static struct rockchip_hdmi_chip_data rk3399_chip_data = {
};

static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = {
- .mode_valid = dw_hdmi_rockchip_mode_valid,
.mpll_cfg = rockchip_mpll_cfg,
.cur_ctr = rockchip_cur_ctr,
.phy_config = rockchip_phy_config,
@@ -557,6 +633,7 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
*/
if (IS_ERR(hdmi->hdmi)) {
ret = PTR_ERR(hdmi->hdmi);
+ devm_kfree(hdmi->dev, hdmi->rates);
drm_encoder_cleanup(encoder);
clk_disable_unprepare(hdmi->vpll_clk);
}
@@ -569,6 +646,7 @@ static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master,
@@ -493,7 +569,6 @@ static struct rockchip_hdmi_chip_data rk3568_chip_data = {
};

static const struct dw_hdmi_plat_data rk3568_hdmi_drv_data = {
- .mode_valid = dw_hdmi_rockchip_mode_valid,
.mpll_cfg = rockchip_mpll_cfg,
.cur_ctr = rockchip_cur_ctr,
.phy_config = rockchip_phy_config,
@@ -623,6 +698,7 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
return 0;

err_bind:
+ devm_kfree(hdmi->dev, hdmi->rates);
drm_encoder_cleanup(encoder);
clk_disable_unprepare(hdmi->ref_clk);
err_clk:
@@ -638,6 +714,7 @@ static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master,
{
struct rockchip_hdmi *hdmi = dev_get_drvdata(dev);

+ devm_kfree(hdmi->dev, hdmi->rates);
dw_hdmi_unbind(hdmi->hdmi);
clk_disable_unprepare(hdmi->vpll_clk);
}
clk_disable_unprepare(hdmi->ref_clk);

--
2.36.1

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