Digital Systems Engineering

Project 1 - Designing a Cache in VHDL

See the project report for a full explanation of the included project files and project requirements.

Name		Name	Last commit message	Last commit date
Latest commit History 4 Commits
_xmsgs		_xmsgs
iseconfig		iseconfig
COE758-Project1.pdf		COE758-Project1.pdf
CPU_gen.bmm		CPU_gen.bmm
CPU_gen.cmd_log		CPU_gen.cmd_log
CPU_gen.spl		CPU_gen.spl
CPU_gen.sym		CPU_gen.sym
CPU_gen.vhd		CPU_gen.vhd
Cache.cmd_log		Cache.cmd_log
Cache.spl		Cache.spl
Cache.sym		Cache.sym
Cache.vhd		Cache.vhd
CacheController.cmd_log		CacheController.cmd_log
CacheController.spl		CacheController.spl
CacheController.sym		CacheController.sym
CacheController.vhd		CacheController.vhd
Cache_summary.html		Cache_summary.html
Project1.cmd_log		Project1.cmd_log
Project1.spl		Project1.spl
Project1.sym		Project1.sym
Project1.vhd		Project1.vhd
Project1_summary.html		Project1_summary.html
README.md		README.md
SDRAMController.cmd_log		SDRAMController.cmd_log
SDRAMController.spl		SDRAMController.spl
SDRAMController.sym		SDRAMController.sym
SDRAMController.vhd		SDRAMController.vhd
d_in_mux.cmd_log		d_in_mux.cmd_log
d_in_mux.spl		d_in_mux.spl
d_in_mux.sym		d_in_mux.sym
d_in_mux.vhd		d_in_mux.vhd
d_in_mux_summary.html		d_in_mux_summary.html
d_out_mux.cmd_log		d_out_mux.cmd_log
d_out_mux.spl		d_out_mux.spl
d_out_mux.sym		d_out_mux.sym
d_out_mux.vhd		d_out_mux.vhd
pepExtractor.prj		pepExtractor.prj
proj1.gise		proj1.gise
proj1.xise		proj1.xise
sram.cmd_log		sram.cmd_log
sram.spl		sram.spl
sram.sym		sram.sym
sram.vhd		sram.vhd