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1. Phase-Locked-Loop-Design-using-SKY130nm-Technology Phase-Locked-Loop-Design-using-SKY130nm-Technology Public

   Workshop, 31 July 2021 and 1 August 2021

   3 6

2. Sky130-VLSI-Workshop Sky130-VLSI-Workshop Public

   Forked from VictorySpecificationII/Sky130-VLSI-Workshop

   VSD-IAT repository for workshop

3. avsdpll_1v8 avsdpll_1v8 Public

   Forked from lakshmi-sathi/avsdpll_1v8

   8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x multiplied clock at ~50% duty cycle on tt corner at room tempe…

4. RTL-design-with-verilog-using-SKY130-Technology RTL-design-with-verilog-using-SKY130-Technology Public

   Forked from Pramod-Krishna/RTL-design-with-verilog-using-SKY130-Technology

5. RTL_Design_and_Synthesis_using_SKY130PDK_Yosys_iVerilog RTL_Design_and_Synthesis_using_SKY130PDK_Yosys_iVerilog Public

   Forked from iamrk-vlsi/RTL_Design_and_Synthesis_using_SKY130PDK_Yosys_iVerilog

   This github repo is to document the 5day "RTL Design and Synthesis using Verilog and Sky130 library" which was conducted by VLSI System Design Corp.

6. github-markdown-toc github-markdown-toc Public

   Forked from ekalinin/github-markdown-toc

   Easy TOC creation for GitHub README.md

   Shell