3700_utils: configure twin-die combined parameters for each topology

name: mv_ddr_twin_die 0 = twin-die combined 1 = single die(regular) Change-Id: I92d1654d0110f43ef0d00079332fa367390c6dc2 Signed-off-by: Moti Buskila <motib@marvell.com> Reviewed-on: https://sj1git1.cavium.com/18458 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
MarvellEmbeddedProcessors · Dec 16, 2020 · 8cb7fbe · 8cb7fbe
1 parent a230070
commit 8cb7fbe
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diff --git a/tim/ddr/DDR_TOPOLOGY_0.txt b/tim/ddr/DDR_TOPOLOGY_0.txt
@@ -21,3 +21,6 @@ ddr_bus_width_index=2
 
 #4Gbits (512MB)
 ddr_mem_size_index=3
+
+#twin-die combined
+ddr_twin_die_index=1
diff --git a/tim/ddr/DDR_TOPOLOGY_1.txt b/tim/ddr/DDR_TOPOLOGY_1.txt
@@ -20,3 +20,6 @@ ddr_bus_width_index=2
 
 #4Gbits (512MB)
 ddr_mem_size_index=3
+
+#twin-die combined
+ddr_twin_die_index=1
diff --git a/tim/ddr/DDR_TOPOLOGY_2.txt b/tim/ddr/DDR_TOPOLOGY_2.txt
@@ -20,3 +20,6 @@ ddr_bus_width_index=2
 
 #4Gbits (512MB)
 ddr_mem_size_index=3
+
+#twin-die combined
+ddr_twin_die_index=1
diff --git a/tim/ddr/DDR_TOPOLOGY_3.txt b/tim/ddr/DDR_TOPOLOGY_3.txt
@@ -20,3 +20,6 @@ ddr_bus_width_index=1
 
 #8Gbits (1GB)
 ddr_mem_size_index=4
+
+#twin-die combined
+ddr_twin_die_index=1
diff --git a/tim/ddr/DDR_TOPOLOGY_4.txt b/tim/ddr/DDR_TOPOLOGY_4.txt
@@ -20,3 +20,6 @@ ddr_bus_width_index=2
 
 #8Gbits (1GB)
 ddr_mem_size_index=4
+
+#twin-die combined
+ddr_twin_die_index=1
diff --git a/tim/ddr/DDR_TOPOLOGY_5.txt b/tim/ddr/DDR_TOPOLOGY_5.txt
@@ -20,3 +20,6 @@ ddr_bus_width_index=2
 
 #8Gbits (1GB)
 ddr_mem_size_index=4
+
+#twin-die combined
+ddr_twin_die_index=1
diff --git a/tim/ddr/DDR_TOPOLOGY_6.txt b/tim/ddr/DDR_TOPOLOGY_6.txt
@@ -20,3 +20,6 @@ ddr_bus_width_index=2
 
 #8Gbits (1GB)
 ddr_mem_size_index=4
+
+#twin-die combined
+ddr_twin_die_index=1
diff --git a/tim/ddr/DDR_TOPOLOGY_CUST.txt b/tim/ddr/DDR_TOPOLOGY_CUST.txt
@@ -21,6 +21,9 @@ ddr_bus_width_index=2
 #4Gbits (512MB)
 ddr_mem_size_index=3
 
+#twin-die combined
+ddr_twin_die_index=1
+
 #800M-1600K(optional)
 ddr_cas_latency=11
-ddr_cas_write_latency=8
+ddr_cas_write_latency=8