fix: clk: ap806: update supported frequency modes

Align all frequency mode entries with most updated SoC specification, including HCLK settings. Supported frequency modes and their Sample at Reset value: 0x0 : CPU@2000Mhz, DDR@1200Mhz, RCLK@1200Mhz 0x1 : CPU@2000Mhz, DDR@1050Mhz, RCLK@1050Mhz 0x4 : CPU@1600Mhz, DDR@800 Mhz, RCLK@800Mhz 0x6 : CPU@1800Mhz, DDR@1200Mhz, RCLK@1200Mhz 0x7 : CPU@1800Mhz, DDR@1050Mhz, RCLK@1050Mhz 0x0d : CPU@1600Mhz, DDR@1050Mhz, RCLK@1050Mhz 0x13 : CPU@1000Mhz, DDR@650Mhz, RCLK@650Mhz 0x14 : CPU@1300Mhz, DDR@800Mhz, RCLK@800Mhz 0x17 : CPU@1300Mhz, DDR@650Mhz, RCLK@650Mhz 0x19 : CPU@1200Mhz, DDR@800Mhz, RCLK@800Mhz 0x1a : CPU@1400Mhz, DDR@800Mhz, RCLK@800Mhz 0x1b : CPU@600Mhz, DDR@800Mhz, RCLK@800Mhz 0x1c : CPU@800Mhz, DDR@800Mhz, RCLK@800Mhz 0x1d : CPU@1000Mhz, DDR@800Mhz, RCLK@800Mhz Change-Id: I55d080373753797a4e7dabb44c6cc3a3760967b6 Signed-off-by: Omri Itach <omrii@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/38462 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Hanna Hawa <hannah@marvell.com>
MarvellEmbeddedProcessors · Apr 27, 2017 · 965d69e · 965d69e
1 parent 46c5e3d
commit 965d69e
Showing 1 changed file with 20 additions and 30 deletions.
diff --git a/drivers/clk/mvebu/ap806-system-controller.c b/drivers/clk/mvebu/ap806-system-controller.c
@@ -56,21 +56,25 @@ static void __init ap806_syscon_clk_init(struct device_node *np)
 	case 0x0 ... 0x1:
 		cpuclk_freq = 2000;
 		break;
+	case 0x6 ... 0x7:
+		cpuclk_freq = 1800;
+		break;
 	case 0x4:
-	case 0xB ... 0x12:
+	case 0xD:
 		cpuclk_freq = 1600;
 		break;
 	case 0x1A:
 		cpuclk_freq = 1400;
 		break;
-	case 0x14 ... 0x18:
+	case 0x14:
+	case 0x17:
 		cpuclk_freq = 1300;
 		break;
 	case 0x19:
 		cpuclk_freq = 1200;
 		break;
-	case 0x13:
 	case 0x1D:
+	case 0x13:
 		cpuclk_freq = 1000;
 		break;
 	case 0x1C:
@@ -85,50 +89,36 @@ static void __init ap806_syscon_clk_init(struct device_node *np)
 		** baudrate of the UART
 		*/
 		cpuclk_freq = 0;
-		pr_err("invalid SAR value\n");
+		pr_err("invalid Sample at Reset value\n");
 	}
 
-	/* Get DCLK frequency */
+	/* Get DCLK frequency (DCLK = 0.5*DDR_CLK) */
 	switch (freq_mode) {
 	case 0x0:
+	case 0x6:
 		dclk_freq = 600;
 		break;
 	case 0x1:
-		dclk_freq = 525;
-		break;
-	case 0x4:
-	case 0x10:
-	case 0x14:
-	case 0x19 ... 0x1D:
-		dclk_freq = 400;
-		break;
-	case 0xC:
-		dclk_freq = 600;
-		break;
+	case 0x7:
 	case 0xD:
-	case 0x16:
 		dclk_freq = 525;
 		break;
-	case 0xB:
-	case 0xE:
-	case 0xF:
-		dclk_freq = 450;
-		break;
-	case 0x12:
 	case 0x13:
 	case 0x17:
 		dclk_freq = 325;
 		break;
-	case 0x11:
-	case 0x15:
-		dclk_freq = 800;
-		break;
-	case 0x18:
-		dclk_freq = 650;
+	case 0x4:
+	case 0x14:
+	case 0x19:
+	case 0x1A:
+	case 0x1B:
+	case 0x1C:
+	case 0x1D:
+		dclk_freq = 400;
 		break;
 	default:
 		dclk_freq = 0;
-		pr_err("invalid SAR value\n");
+		pr_err("invalid Sample at Reset value\n");
 	}
 
 	/* Convert to hertz */