mv_ddr: ddr3: only use active chip-selects when tuning ODT #18
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cpackham
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Feb 27, 2019
Inactive chip-selects will give invalid values for read_sample so don't consider them when trying to determine the overall min/max read sample. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
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Mar 19, 2019
Inactive chip-selects will give invalid values for read_sample so don't consider them when trying to determine the overall min/max read sample. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> [MarvellEmbeddedProcessors/mv-ddr-marvell#18] Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
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This pull request was already merged by commit a87f4f7e81cef3afba0a002ab5d031dbffc9fa22 into master branch. |
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On boards with particularly short traces the read sampling can end up 0
which can end up configuring an excessively long ODT read delay due to
the integer underflow of 'min_read_sample - 1'. When the read sampling
in ddr3_tip_write_additional_odt_setting gets a value lower than cas_l
make cas_l the minimum.
Signed-off-by: Chris Packham chris.packham@alliedtelesis.co.nz