stm8.cfg

; The format of the input file:
; each device definition begins with a line like this:
;
;       .devicename
;
;  after it go the port definitions in this format:
;
;       portname        address
;
;  the bit definitions (optional) are represented like this:
;
;       portname.bitname  bitnumber
;
; lines beginning with a space are ignored.
; comment lines should be started with ';' character.
;
; the default device is specified at the start of the file
;
;       .default device_name
;
; all lines non conforming to the format are passed to the callback function
;
; ST7 FAMILY SPECIFIC LINES
;------------------------
;
; the processor definition may include the memory configuration.
; the line format is:

;       area CLASS AREA-NAME START:END
;
; where CLASS is anything, but please use one of CODE, DATA, BSS
;       START and END are addresses, the end address is not included

; Interrupt vectors are declared in the following way:

; entry NAME ADDRESS COMMENT

.default STM8L151x8

.STM8L151x8
; http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATASHEET/CD00284933.pdf
; 4Kbytes RAM - 0x0000:0x0FFF
; 32Kbytes Flash? - 0x8000:0xFFFF

; XXX - TODO - end address not included
; MEMORY MAP
area DATA RAM            0x00000:0x01000
area DATA EEPROM         0x01000:0x01800
area BSS RESERVED        0x01800:0x04800
area DATA OPTION_BYTES   0x04800:0x04900
area BSS RESERVED        0x04900:0x04910
area DATA VREFINT        0x04910:0x04911
area DATA TSFACTORY      0x04911:0x04912
area DATA RESERVED       0x04912:0x04926
area DATA UNIQUEID       0x04926:0x04932
area DATA RESERVED       0x04932:0x05000
area DATA GPIOS          0x05000:0x05800
area BSS RESERVED        0x05800:0x06000
area DATA BOOTROM        0x06000:0x06800
area BSS RESERVED        0x06800:0x07F00
area DATA REGS1          0x07F00:0x08000
;area CODE VECS1          0x08000:0x08080
;area CODE CODE1          0x08080:0x09000
;area CODE VECS2          0x09000:0x09080
;area CODE CODE2          0x09080:0x20000


; Interrupt and reset vector assignments
entry __RESET              0x9000   Reset
entry TRAP_                0x9004   TRAP (software) Interrupt Vector
entry TLI_                 0x9008   External Top Level Interrupt
entry FLASH_               0x900C   EOP/WR_PG_DIS
entry DMA1_0_1             0x9010   DMA1 channels 0/1
entry DMA1_2_3             0x9014   DMA1 channels 2/3
entry RTC_LSE_CSS          0x9018   RTC alarm interrupt/LSE CSS interrupt
entry EXTI_E_F_PVD         0x901C   PortE/F interrupt/PVD interrupt
entry EXTI_B_G             0x9020   External interrupt port B/G
entry EXTI_D_H             0x9024   External interrupt port D/H
entry EXTI0                0x9028   External interrupt 0
entry EXTI1                0x902C   External interrupt 1
entry EXTI2                0x9030   External interrupt 2
entry EXTI3                0x9034   External interrupt 3
entry EXTI4                0x9038   External interrupt 4
entry EXTI5                0x903C   External interrupt 5
entry EXTI6                0x9040   External interrupt 6
entry EXTI7                0x9044   External interrupt 7
entry LCD                  0x9048   LCD interrupt
entry CLK_TIM1_DAC         0x904C   System clock switch/CSS interrupt/TIM1 break/DAC
entry COMP1_COMP2_ADC1     0x9050   Comparator 1 and 2 interrupt/ADC1
entry TIM2_USART2          0x9054   TIM2 update/overflow/trigger/break/USART2 transmission complete/transmit data register empty interrupt
entry TIM2_USART2_         0x9058   Capture/Compare/USART2 interrupt
entry TIM3_USART3          0x905C   TIM3 Update /Overflow/Trigger/Break/USART3 transmission complete/transmit data register empty interrupt
entry TIM3_USART3_         0x9060   TIM3 Capture/Compare/USART3 Receive register data full/overrun/idle line detected/parity error/interrupt
entry TIM1                 0x9064   Update /overflow/trigger/COM
entry TIM1_                0x9068   Capture/Compare
entry TIM4                 0x906C   Update/overflow/trigger
entry SPI1                 0x9070   End of Transfer
entry USART1_TIM5          0x9074   USART1 transmission complete/transmit data register empty/TIM5 update/overflow/trigger/break
entry USART1_TIM5_         0x9078   USART1 Receive register data full/overrun/idle line detected/parity error/TIM5 capture/compare
entry I2C1_SPI2            0x907C   I2C1 interrupt(5)/SPI2

;interrupt __RESET    0xFFFE   Reset
;interrupt TRAP_      0xFFFC   TRAP (software) Interrupt Vector
;interrupt EI0_       0xFFFA   External Interrupt Vector EI0
;interrupt EI1_       0xFFF8   External Interrupt Vector EI1
;interrupt SPI_       0xFFF4   SPI Interrupt Vector
;interrupt TIMER_A    0xFFF2   TIMER A Interrupt Vector
;interrupt TIMER_B    0xFFEE   TIMER B Interrupt Vector (ST72212 only)


; INPUT/OUTPUT PORTS

;/* Port A */
;/*****************************************************************/
PA_ODR 0x5000 Port A data output latch register
PA_IDR 0x5001 Port A input pin value register
PA_DDR 0x5002 Port A data direction register
PA_CR1 0x5003 Port A control register 1
PA_CR2 0x5004 Port A control register 2

;/* Port B */
;/*****************************************************************/
PB_ODR 0x5005 Port B data output latch register
PB_IDR 0x5006 Port B input pin value register
PB_DDR 0x5007 Port B data direction register
PB_CR1 0x5008 Port B control register 1
PB_CR2 0x5009 Port B control register 2

;/* Port C */
;/*****************************************************************/
PC_ODR 0x500a Port C data output latch register
PC_IDR 0x500b Port C input pin value register
PC_DDR 0x500c Port C data direction register
PC_CR1 0x500d Port C control register 1
PC_CR2 0x500e Port C control register 2

;/* Port D */
;/*****************************************************************/
PD_ODR 0x500f Port D data output latch register
PD_IDR 0x5010 Port D input pin value register
PD_DDR 0x5011 Port D data direction register
PD_CR1 0x5012 Port D control register 1
PD_CR2 0x5013 Port D control register 2

;/* Port E */
;/*****************************************************************/
PE_ODR 0x5014 Port E data output latch register
PE_IDR 0x5015 Port E input pin value register
PE_DDR 0x5016 Port E data direction register
PE_CR1 0x5017 Port E control register 1
PE_CR2 0x5018 Port E control register 2

;/* Port F */
;/*****************************************************************/
PF_ODR 0x5019 Port F data output latch register
PF_IDR 0x501a Port F input pin value register
PF_DDR 0x501b Port F data direction register
PF_CR1 0x501c Port F control register 1
PF_CR2 0x501d Port F control register 2

;/* Port G */
;/*****************************************************************/
PG_ODR 0x501e Port G data output latch register
PG_IDR 0x501f Port G input pin value register
PG_DDR 0x5020 Port G data direction register
PG_CR1 0x5021 Port G control register 1
PG_CR2 0x5022 Port G control register 2

;/* Flash */
;/*****************************************************************/
FLASH_CR1   0x5050 Flash control register 1
FLASH_CR2   0x5051 Flash control register 2
FLASH_PUKR  0x5052 Flash Program memory unprotection register
FLASH_DUKR  0x5053 Data EEPROM unprotection register
FLASH_IAPSR 0x5054 Flash in-application programming status register

;/* Direct memory access controller 1 (DMA1) */
;/*****************************************************************/
DMA1_GCSR           0x5070 DMA1 global configuration & status register
DMA1_GIR1           0x5071 DMA1 global interrupt register 1
DMA1_C0CR           0x5075 DMA1 channel 0 configuration register
DMA1_C0SPR          0x5076 DMA1 channel 0 status & priority register
DMA1_C0NDTR         0x5077 DMA1 number of data to transfer register (channel 0)
DMA1_C0PAR          0x5078 DMA1 peripheral address register (channel 0)
;DMA1_C0PARH         0x5078 DMA peripheral address high register (channel 0)
;DMA1_C0PARL         0x5079 DMA peripheral address low register (channel 0)
DMA1_C0M0AR         0x507b DMA1 memory 0 address register (channel 0)
;DMA1_C0M0ARH        0x507b DMA memory address high register (channel 0)
;DMA1_C0M0ARL        0x507c DMA memory address low register (channel 0)
DMA1_C1CR           0x507f DMA1 channel 1 configuration register
DMA1_C1SPR          0x5080 DMA1 channel 1 status & priority register
DMA1_C1NDTR         0x5081 DMA1 number of data to transfer register (channel 1)
DMA1_C1PAR          0x5082 DMA1 peripheral address register (channel 1)
;DMA1_C1PARH         0x5082 DMA peripheral address high register (channel 1)
;DMA1_C1PARL         0x5083 DMA peripheral address low register (channel 1)
DMA1_C1M0AR         0x5085 DMA1 memory 0 address register (channel 1)
;DMA1_C1M0ARH        0x5085 DMA memory address high register (channel 1)
;DMA1_C1M0ARL        0x5086 DMA memory address low register (channel 1)
DMA1_C2CR           0x5089 DMA1 channel 2 configuration register
DMA1_C2SPR          0x508a DMA1 channel 2 status & priority register
DMA1_C2NDTR         0x508b DMA1 number of data to transfer register (channel 2)
DMA1_C2PAR          0x508c DMA1 peripheral address register (channel 2)
;DMA1_C2PARH         0x508c DMA peripheral address high register (channel 2)
;DMA1_C2PARL         0x508d DMA peripheral address low register (channel 2)
DMA1_C2M0AR         0x508f DMA1 memory 0 address register (channel 2)
;DMA1_C2M0ARH        0x508f DMA memory address high register (channel 2)
;DMA1_C2M0ARL        0x5090 DMA memory address low register (channel 2)
DMA1_C3CR           0x5093 DMA1 channel 3 configuration register
DMA1_C3SPR          0x5094 DMA1 channel 3 status & priority register
DMA1_C3NDTR         0x5095 DMA1 number of data to transfer register (channel 3)
DMA1_C3PAR_C3M1AR   0x5096 DMA1 peripheral address register (channel 3)
;DMA1_C3PARH_C3M1ARH 0x5096 DMA1 peripheral address high register (channel 3)
;DMA1_C3PARL_C3M1ARL 0x5097 DMA1 peripheral address low register (channel 3)
DMA_C3M0EAR         0x5098 DMA channel 3 memory 0 extended address register
DMA1_C3M0AR         0x5099 DMA1 memory 0 address register (channel 3)
;DMA1_C3M0ARH        0x5099 DMA memory address high register (channel 3)
;DMA1_C3M0ARL        0x509a DMA memory address low register (channel 3)

;/* System configuration (SYSCFG) */
;/*****************************************************************/
SYSCFG_RMPCR3 0x509d Remapping register 3
SYSCFG_RMPCR1 0x509e Remapping register 1
SYSCFG_RMPCR2 0x509f Remapping register 2

;/* External Interrupt Control Register (ITC) */
;/*****************************************************************/
EXTI_CR1   0x50a0 External interrupt control register 1
EXTI_CR2   0x50a1 External interrupt control register 2
EXTI_CR3   0x50a2 External interrupt control register 3
EXTI_SR1   0x50a3 External interrupt status register 1
EXTI_SR2   0x50a4 External interrupt status register 2
EXTI_CONF1 0x50a5 External interrupt port select register 1

;/* Wait For Event (WFE) */
;/*****************************************************************/
WFE_CR1 0x50a6 WFE control register 1
WFE_CR2 0x50a7 WFE control register 2
WFE_CR3 0x50a8 WFE control register 3
WFE_CR4 0x50a9 WFE control register 4

;/* External Interrupt Control Register (ITC) */
;/*****************************************************************/
EXTI_CR4   0x50aa External interrupt control register 4
EXTI_CONF2 0x50ab External interrupt port select register 2

;/* Reset (RST) */
;/*****************************************************************/
RST_CR 0x50b0 Reset control register
RST_SR 0x50b1 Reset status register

;/* Power control (PWR) */
;/*****************************************************************/
PWR_CSR1 0x50b2 Power control and status register 1
PWR_CSR2 0x50b3 Power control and status register 2

;/* Clock Control (CLK) */
;/*****************************************************************/
CLK_CKDIVR    0x50c0 System clock divider register
CLK_CRTCR     0x50c1 Clock RTC register
CLK_ICKCR     0x50c2 Internal clock control register
CLK_PCKENR1   0x50c3 Peripheral clock gating register 1
CLK_PCKENR2   0x50c4 Peripheral clock gating register 2
CLK_CCOR      0x50c5 Configurable clock control register
CLK_ECKCR     0x50c6 External clock control register
CLK_SCSR      0x50c7 System clock status register
CLK_SWR       0x50c8 System clock switch register
CLK_SWCR      0x50c9 Clock switch control register
CLK_CSSR      0x50ca Clock security system register
CLK_CBEEPR    0x50cb Clock BEEP register
CLK_HSICALR   0x50cc HSI calibration register
CLK_HSITRIMR  0x50cd HSI clock calibration trimming register
CLK_HSIUNLCKR 0x50ce HSI unlock register
CLK_REGCSR    0x50cf Main regulator control status register
CLK_PCKENR3   0x50d0 Peripheral clock gating register 3

;/* Window Watchdog (WWDG) */
;/*****************************************************************/
WWDG_CR 0x50d3 WWDG Control Register
WWDG_WR 0x50d4 WWDR Window Register

;/* Independent Watchdog (IWDG) */
;/*****************************************************************/
IWDG_KR  0x50e0 IWDG Key Register
IWDG_PR  0x50e1 IWDG Prescaler Register
IWDG_RLR 0x50e2 IWDG Reload Register

;/* Beeper (BEEP) */
;/*****************************************************************/
BEEP_CSR1 0x50f0 BEEP Control/Status Register 1
BEEP_CSR2 0x50f3 BEEP Control/Status Register 2

;/* Real-time clock (RTC) */
;/*****************************************************************/
RTC_TR1         0x5140 Time Register 1
RTC_TR2         0x5141 Time Register 2
RTC_TR3         0x5142 Time Register 3
RTC_DR1         0x5144 Date Register 1
RTC_DR2         0x5145 Date Register 2
RTC_DR3         0x5146 Date Register 3
RTC_CR1         0x5148 Control Register 1
RTC_CR2         0x5149 Control Register 2
RTC_CR3         0x514a Control Register 3
RTC_ISR1        0x514c Initialization and Status Register 1
RTC_ISR2        0x514d Initialization and Status Register 2
RTC_SPRER       0x5150 Synchronous Prescaler Register
;RTC_SPRERH      0x5150 Synchronous Prescaler Register High
;RTC_SPRERL      0x5151 Synchronous Prescaler Register Low
RTC_APRER       0x5152 Asynchronous Prescaler Register
RTC_WUTR        0x5154 Wakeup Timer Register
;RTC_WUTRH       0x5154 Wakeup Timer Register High
;RTC_WUTRL       0x5155 Wakeup Timer Register Low
RTC_SSR         0x5157 Subsecond Register
;RTC_SSRH        0x5157 Subsecond Register High
;RTC_SSRL        0x5158 Subsecond Register Low
RTC_WPR         0x5159 Write Protection Register
RTC_SHIFTR      0x515a Shift Register
;RTC_SHIFTRH     0x515a Shift Register High
;RTC_SHIFTRL     0x515b Shift Register Low
RTC_ALRMAR1     0x515c Alarm A Register 1
RTC_ALRMAR2     0x515d Alarm A Register 2
RTC_ALRMAR3     0x515e Alarm A Register 3
RTC_ALRMAR4     0x515f Alarm A Register 4
RTC_ALRMASSR    0x5164 Alarm A subsecond Register
;RTC_ALRMASSRH   0x5164 Shift Register High
;RTC_ALRMASSRL   0x5165 Shift Register Low
RTC_ALRMASSMSKR 0x5166 Alarm A masking Register
RTC_CALR        0x516a Calibration Register
;RTC_CALRH       0x516a Shift Register High
;RTC_CALRL       0x516b Shift Register Low
RTC_TCR1        0x516c Tamper Control Register 1
RTC_TCR2        0x516d Tamper Control Register 2

;/* Clock Security System (LSE_CSS) */
;/*****************************************************************/
CSS_LSE_CSR 0x5190 CSS on LSE Control and Status Register

;/* Serial Peripheral Interface 1 (SPI1) */
;/*****************************************************************/
SPI1_CR1    0x5200 SPI1 Control Register 1
SPI1_CR2    0x5201 SPI1 Control Register 2
SPI1_ICR    0x5202 SPI1 Interrupt Control Register
SPI1_SR     0x5203 SPI1 Status Register
SPI1_DR     0x5204 SPI1 Data Register
SPI1_CRCPR  0x5205 SPI1 CRC Polynomial Register
SPI1_RXCRCR 0x5206 SPI1 Rx CRC Register
SPI1_TXCRCR 0x5207 SPI1 Tx CRC Register

;/* I2C Bus Interface 1 (I2C1) */
;/*****************************************************************/
I2C1_CR1    0x5210 I2C1 control register 1
I2C1_CR2    0x5211 I2C1 control register 2
I2C1_FREQR  0x5212 I2C1 frequency register
I2C1_OARL   0x5213 I2C1 Own address register low
I2C1_OARH   0x5214 I2C1 Own address register high
I2C1_OAR2   0x5215 I2C1 Own address register for dual mode
I2C1_DR     0x5216 I2C1 data register
I2C1_SR1    0x5217 I2C1 status register 1
I2C1_SR2    0x5218 I2C1 status register 2
I2C1_SR3    0x5219 I2C1 status register 3
I2C1_ITR    0x521a I2C1 interrupt control register
I2C1_CCRL   0x521b I2C1 Clock control register low
I2C1_CCRH   0x521c I2C1 Clock control register high
I2C1_TRISER 0x521d I2C1 TRISE register
I2C1_PECR   0x521e I2C1 packet error checking register

;/* Universal synch/asynch receiver transmitter 1 (USART1) */
;/*****************************************************************/
USART1_SR   0x5230 USART1 Status Register
USART1_DR   0x5231 USART1 Data Register
USART1_BRR1 0x5232 USART1 Baud Rate Register 1
USART1_BRR2 0x5233 USART1 Baud Rate Register 2
USART1_CR1  0x5234 USART1 Control Register 1
USART1_CR2  0x5235 USART1 Control Register 2
USART1_CR3  0x5236 USART1 Control Register 3
USART1_CR4  0x5237 USART1 Control Register 4
USART1_CR5  0x5238 USART1 Control Register 5
USART1_GTR  0x5239 USART1 Guard time Register
USART1_PSCR 0x523a USART1 Prescaler Register

;/* 16-Bit Timer 2 (TIM2) */
;/*****************************************************************/
TIM2_CR1   0x5250 TIM2 Control register 1
TIM2_CR2   0x5251 TIM2 Control register 2
TIM2_SMCR  0x5252 TIM2 Slave Mode Control register
TIM2_ETR   0x5253 TIM2 External trigger register
TIM2_DER   0x5254 TIM2 DMA request enable register
TIM2_IER   0x5255 TIM2 Interrupt enable register
TIM2_SR1   0x5256 TIM2 Status register 1
TIM2_SR2   0x5257 TIM2 Status register 2
TIM2_EGR   0x5258 TIM2 Event Generation register
TIM2_CCMR1 0x5259 TIM2 Capture/Compare mode register 1
TIM2_CCMR2 0x525a TIM2 Capture/Compare mode register 2
TIM2_CCER1 0x525b TIM2 Capture/Compare enable register 1
TIM2_CNTR  0x525c TIM2 Counter
;TIM2_CNTRH 0x525c TIM2 Counter High
;TIM2_CNTRL 0x525d TIM2 Counter Low
TIM2_PSCR  0x525e TIM2 Prescaler register
TIM2_ARR   0x525f TIM2 Auto-reload register
;TIM2_ARRH  0x525f TIM2 Auto-Reload Register High
;TIM2_ARRL  0x5260 TIM2 Auto-Reload Register Low
TIM2_CCR1  0x5261 TIM2 Capture/Compare register 1
;TIM2_CCR1H 0x5261 TIM2 Capture/Compare Register 1 High
;TIM2_CCR1L 0x5262 TIM2 Capture/Compare Register 1 Low
TIM2_CCR2  0x5263 TIM2 Capture/Compare register 2
;TIM2_CCR2H 0x5263 TIM2 Capture/Compare Register 2 High
;TIM2_CCR2L 0x5264 TIM2 Capture/Compare Register 2 Low
TIM2_BKR   0x5265 TIM2 Break register
TIM2_OISR  0x5266 TIM2 Output idle state register

;/* 16-Bit Timer 3 (TIM3) */
;/*****************************************************************/
TIM3_CR1   0x5280 TIM3 Control register 1
TIM3_CR2   0x5281 TIM3 Control register 2
TIM3_SMCR  0x5282 TIM3 Slave Mode Control register
TIM3_ETR   0x5283 TIM3 External trigger register
TIM3_DER   0x5284 TIM3 DMA request enable register
TIM3_IER   0x5285 TIM3 Interrupt enable register
TIM3_SR1   0x5286 TIM3 Status register 1
TIM3_SR2   0x5287 TIM3 Status register 2
TIM3_EGR   0x5288 TIM3 Event Generation register
TIM3_CCMR1 0x5289 TIM3 Capture/Compare mode register 1
TIM3_CCMR2 0x528a TIM3 Capture/Compare mode register 2
TIM3_CCER1 0x528b TIM3 Capture/Compare enable register 1
TIM3_CNTR  0x528c TIM3 Counter
;TIM3_CNTRH 0x528c TIM3 Counter High
;TIM3_CNTRL 0x528d TIM3 Counter Low
TIM3_PSCR  0x528e TIM3 Prescaler register
TIM3_ARR   0x528f TIM3 Auto-reload register
;TIM3_ARRH  0x528f TIM3 Auto-Reload Register High
;TIM3_ARRL  0x5290 TIM3 Auto-Reload Register Low
TIM3_CCR1  0x5291 TIM3 Capture/Compare register 1
;TIM3_CCR1H 0x5291 TIM3 Capture/Compare Register 1 High
;TIM3_CCR1L 0x5292 TIM3 Capture/Compare Register 1 Low
TIM3_CCR2  0x5293 TIM3 Capture/Compare register 2
;TIM3_CCR2H 0x5293 TIM3 Capture/Compare Register 2 High
;TIM3_CCR2L 0x5294 TIM3 Capture/Compare Register 2 Low
TIM3_BKR   0x5295 TIM3 Break register
TIM3_OISR  0x5296 TIM3 Output idle state register

;/* 16-Bit Timer 1 (TIM1) */
;/*****************************************************************/
TIM1_CR1   0x52b0 TIM1 Control register 1
TIM1_CR2   0x52b1 TIM1 Control register 2
TIM1_SMCR  0x52b2 TIM1 Slave Mode Control register
TIM1_ETR   0x52b3 TIM1 external trigger register
TIM1_DER   0x52b4 TIM1 DMA request enable register
TIM1_IER   0x52b5 TIM1 Interrupt enable register
TIM1_SR1   0x52b6 TIM1 Status register 1
TIM1_SR2   0x52b7 TIM1 Status register 2
TIM1_EGR   0x52b8 TIM1 Event Generation register
TIM1_CCMR1 0x52b9 TIM1 Capture/Compare mode register 1
TIM1_CCMR2 0x52ba TIM1 Capture/Compare mode register 2
TIM1_CCMR3 0x52bb TIM1 Capture/Compare mode register 3
TIM1_CCMR4 0x52bc TIM1 Capture/Compare mode register 4
TIM1_CCER1 0x52bd TIM1 Capture/Compare enable register 1
TIM1_CCER2 0x52be TIM1 Capture/Compare enable register 2
TIM1_CNTR  0x52bf TIM1 Counter
;TIM1_CNTRH 0x52bf TIM1 Counter High
;TIM1_CNTRL 0x52c0 TIM1 Counter Low
TIM1_PSCR  0x52c1 TIM1 Prescaler register
;TIM1_PSCRH 0x52c1 TIM1 Prescaler Register High
;TIM1_PSCRL 0x52c2 TIM1 Prescaler Register Low
TIM1_ARR   0x52c3 TIM1 Auto-reload register
;TIM1_ARRH  0x52c3 TIM1 Auto-Reload Register High
;TIM1_ARRL  0x52c4 TIM1 Auto-Reload Register Low
TIM1_RCR   0x52c5 TIM1 Repetition counter register
TIM1_CCR1  0x52c6 TIM1 Capture/Compare register 1
;TIM1_CCR1H 0x52c6 TIM1 Capture/Compare Register 1 High
;TIM1_CCR1L 0x52c7 TIM1 Capture/Compare Register 1 Low
TIM1_CCR2  0x52c8 TIM1 Capture/Compare register 2
;TIM1_CCR2H 0x52c8 TIM1 Capture/Compare Register 2 High
;TIM1_CCR2L 0x52c9 TIM1 Capture/Compare Register 2 Low
TIM1_CCR3  0x52ca TIM1 Capture/Compare register 3
;TIM1_CCR3H 0x52ca TIM1 Capture/Compare Register 3 High
;TIM1_CCR3L 0x52cb TIM1 Capture/Compare Register 3 Low
TIM1_CCR4  0x52cc TIM1 Capture/Compare register 4
;TIM1_CCR4H 0x52cc TIM1 Capture/Compare Register 4 High
;TIM1_CCR4L 0x52cd TIM1 Capture/Compare Register 4 Low
TIM1_BKR   0x52ce TIM1 Break register
TIM1_DTR   0x52cf TIM1 Dead-time register
TIM1_OISR  0x52d0 TIM1 Output idle state register
TIM1_DCR1  0x52d1 TIM1 DMA1 control register 1
TIM1_DCR2  0x52d2 TIM1 DMA1 control register 2
TIM1_DMA1R 0x52d3 TIM1 DMA1 address for burst mode

;/* 8-Bit  Timer 4 (TIM4) */
;/*****************************************************************/
TIM4_CR1  0x52e0 TIM4 Control Register 1
TIM4_CR2  0x52e1 TIM4 Control Register 2
TIM4_SMCR 0x52e2 TIM4 Slave Mode Control Register
TIM4_DER  0x52e3 TIM4 DMA request Enable Register
TIM4_IER  0x52e4 TIM4 Interrupt Enable Register
TIM4_SR1  0x52e5 TIM4 Status Register 1
TIM4_EGR  0x52e6 TIM4 Event Generation Register
TIM4_CNTR 0x52e7 TIM4 Counter
TIM4_PSCR 0x52e8 TIM4 Prescaler Register
TIM4_ARR  0x52e9 TIM4 Auto-Reload Register

;/* Infra Red Interface (IR) */
;/*****************************************************************/
IR_CR 0x52ff Infra-red control register

;/* 16-Bit  Timer 5 (TIM5) */
;/*****************************************************************/
TIM5_CR1   0x5300 TIM5 Control register 1
TIM5_CR2   0x5301 TIM5 Control register 2
TIM5_SMCR  0x5302 TIM5 Slave Mode Control register
TIM5_ETR   0x5303 TIM5 External trigger register
TIM5_DER   0x5304 TIM5 DMA request enable register
TIM5_IER   0x5305 TIM5 Interrupt enable register
TIM5_SR1   0x5306 TIM5 Status register 1
TIM5_SR2   0x5307 TIM5 Status register 2
TIM5_EGR   0x5308 TIM5 Event Generation register
TIM5_CCMR1 0x5309 TIM5 Capture/Compare mode register 1
TIM5_CCMR2 0x530a TIM5 Capture/Compare mode register 2
TIM5_CCER1 0x530b TIM5 Capture/Compare enable register 1
TIM5_CNTR  0x530c TIM5 Counter
;TIM5_CNTRH 0x530c TIM5 Counter High
;TIM5_CNTRL 0x530d TIM5 Counter Low
TIM5_PSCR  0x530e TIM5 Prescaler register
TIM5_ARR   0x530f TIM5 Auto-reload register
;TIM5_ARRH  0x530f TIM5 Auto-Reload Register High
;TIM5_ARRL  0x5310 TIM5 Auto-Reload Register Low
TIM5_CCR1  0x5311 TIM5 Capture/Compare register 1
;TIM5_CCR1H 0x5311 TIM5 Capture/Compare Register 1 High
;TIM5_CCR1L 0x5312 TIM5 Capture/Compare Register 1 Low
TIM5_CCR2  0x5313 TIM5 Capture/Compare register 2
;TIM5_CCR2H 0x5313 TIM5 Capture/Compare Register 2 High
;TIM5_CCR2L 0x5314 TIM5 Capture/Compare Register 2 Low
TIM5_BKR   0x5315 TIM5 Break register
TIM5_OISR  0x5316 TIM5 Output idle state register

;/* Analog to digital converter 1 (ADC1) */
;/*****************************************************************/
ADC1_CR1    0x5340 ADC1 Configuration register 1
ADC1_CR2    0x5341 ADC1 Configuration register 2
ADC1_CR3    0x5342 ADC1 Configuration register 3
ADC1_SR     0x5343 ADC1 status register
ADC1_DR     0x5344 ADC1 Data register
;ADC1_DRH    0x5344 ADC Data Register High
;ADC1_DRL    0x5345 ADC Data Register Low
ADC1_HTR    0x5346 ADC1 high threshold register
;ADC1_HTRH   0x5346 ADC High Threshold Register High
;ADC1_HTRL   0x5347 ADC High Threshold Register Low
ADC1_LTR    0x5348 ADC1 low threshold register
;ADC1_LTRH   0x5348 ADC Low Threshold Register High
;ADC1_LTRL   0x5349 ADC Low Threshold Register Low
ADC1_SQR1   0x534a ADC1 channel sequence 1 register
ADC1_SQR2   0x534b ADC1 channel sequence 2 register
ADC1_SQR3   0x534c ADC1 channel sequence 3 register
ADC1_SQR4   0x534d ADC1 channel sequence 4 register
ADC1_TRIGR1 0x534e ADC1 Trigger disable 1
ADC1_TRIGR2 0x534f ADC1 Trigger disable 2
ADC1_TRIGR3 0x5350 ADC1 Trigger disable 3
ADC1_TRIGR4 0x5351 ADC1 Trigger disable 4

;/* Digital to analog converter (DAC) */
;/*****************************************************************/
DAC_CH1CR1    0x5380 DAC channel 1 control register 1
DAC_CH1CR2    0x5381 DAC channel 1 control register 2
DAC_CH2CR1    0x5382 DAC channel 2 control register 1
DAC_CH2CR2    0x5383 DAC channel 2 control register 2
DAC_SWTRIGR   0x5384 DAC software trigger register
DAC_SR        0x5385 DAC status register
DAC_CH1RDHR   0x5388 DAC channel 1 right aligned data holding register
;DAC_CH1RDHRH  0x5388 DAC channel 1 right aligned data holding register high
;DAC_CH1RDHRL  0x5389 DAC channel 1 right aligned data holding register low
DAC_CH1LDHR   0x538c DAC channel 1 left aligned data holding register
;DAC_CH1LDHRH  0x538c DAC channel 1 left aligned data holding register high
;DAC_CH1LDHRL  0x538d DAC channel 1 left aligned data holding register low
DAC_CH1DHR8   0x5390 DAC channel 1 8-bit data holding register
DAC_CH2RDHR   0x5394 DAC channel 2 right aligned data holding register
;DAC_CH2RDHRH  0x5394 DAC channel 2 right aligned data holding register high
;DAC_CH2RDHRL  0x5395 DAC channel 2 right aligned data holding register low
DAC_CH2LDHR   0x5398 DAC channel 2 left aligned data holding register
;DAC_CH2LDHRH  0x5398 DAC channel 2 left aligned data holding register high
;DAC_CH2LDHRL  0x5399 DAC channel 2 left aligned data holding register low
DAC_CH2DHR8   0x539c DAC channel 2 8-bit data holding register
DAC_DCH1RDHR  0x53a0 DAC channel 1 right aligned data holding register
;DAC_DCH1RDHRH 0x53a0 DAC channel 1 right aligned data holding register high
;DAC_DCH1RDHRL 0x53a1 DAC channel 1 right aligned data holding register low
DAC_DCH2RDHR  0x53a2 DAC channel 2 right aligned data holding register
;DAC_DCH2RDHRH 0x53a2 DAC channel 2 right aligned data holding register high
;DAC_DCH2RDHRL 0x53a3 DAC channel 2 right aligned data holding register low
DAC_DCH1LDHR  0x53a4 DAC channel 1 left aligned data holding register
;DAC_DCH1LDHRH 0x53a4 DAC channel 1 left aligned data holding register high
;DAC_DCH1LDHRL 0x53a5 DAC channel 1 left aligned data holding register low
DAC_DCH2LDHR  0x53a6 DAC channel 2 left aligned data holding register
;DAC_DCH2LDHRH 0x53a6 DAC channel 2 left aligned data holding register high
;DAC_DCH2LDHRL 0x53a7 DAC channel 2 left aligned data holding register low
DAC_DCH1DHR8  0x53a8 DAC channel 1 8-bit data holding register
DAC_DCH2DHR8  0x53a9 DAC channel 2 8-bit data holding register
DAC_CH1DOR    0x53ac DAC channel 1 data output register
;DAC_CH1DORH   0x53ac DAC channel 1 data output register high
;DAC_CH1DORL   0x53ad DAC channel 1 data output register low
DAC_CH2DOR    0x53b0 DAC channel 2 data output register
;DAC_CH2DORH   0x53b0 DAC channel 2 data output register high
;DAC_CH2DORL   0x53b1 DAC channel 2 data output register low

;/* Serial Peripheral Interface 2 (SPI2) */
;/*****************************************************************/
SPI2_CR1    0x53c0 SPI2 Control Register 1
SPI2_CR2    0x53c1 SPI2 Control Register 2
SPI2_ICR    0x53c2 SPI2 Interrupt Control Register
SPI2_SR     0x53c3 SPI2 Status Register
SPI2_DR     0x53c4 SPI2 Data Register
SPI2_CRCPR  0x53c5 SPI2 CRC Polynomial Register
SPI2_RXCRCR 0x53c6 SPI2 Rx CRC Register
SPI2_TXCRCR 0x53c7 SPI2 Tx CRC Register

;/* Universal synch/asynch receiver transmitter 2 (USART2) */
;/*****************************************************************/
USART2_SR   0x53e0 USART2 Status Register
USART2_DR   0x53e1 USART2 Data Register
USART2_BRR1 0x53e2 USART2 Baud Rate Register 1
USART2_BRR2 0x53e3 USART2 Baud Rate Register 2
USART2_CR1  0x53e4 USART2 Control Register 1
USART2_CR2  0x53e5 USART2 Control Register 2
USART2_CR3  0x53e6 USART2 Control Register 3
USART2_CR4  0x53e7 USART2 Control Register 4
USART2_CR5  0x53e8 USART2 Control Register 5
USART2_GTR  0x53e9 USART2 Guard time Register
USART2_PSCR 0x53ea USART2 Prescaler Register

;/* Universal synch/asynch receiver transmitter 3 (USART3) */
;/*****************************************************************/
USART3_SR   0x53f0 USART3 Status Register
USART3_DR   0x53f1 USART3 Data Register
USART3_BRR1 0x53f2 USART3 Baud Rate Register 1
USART3_BRR2 0x53f3 USART3 Baud Rate Register 2
USART3_CR1  0x53f4 USART3 Control Register 1
USART3_CR2  0x53f5 USART3 Control Register 2
USART3_CR3  0x53f6 USART3 Control Register 3
USART3_CR4  0x53f7 USART3 Control Register 4
USART3_CR5  0x53f8 USART3 Control Register 5
USART3_GTR  0x53f9 USART3 Guard time Register
USART3_PSCR 0x53fa USART3 Prescaler Register

;/* Routing interface (RI) */
;/*****************************************************************/
RI_ICR1   0x5431 Timer input capture routing register 1
RI_ICR2   0x5432 Timer input capture routing register 2
RI_IOIR1  0x5433 I/O input register 1
RI_IOIR2  0x5434 I/O input register 2
RI_IOIR3  0x5435 I/O input register 3
RI_IOCMR1 0x5436 I/O control mode register 1
RI_IOCMR2 0x5437 I/O control mode register 2
RI_IOCMR3 0x5438 I/O control mode register 3
RI_IOSR1  0x5439 I/O switch register 1
RI_IOSR2  0x543a I/O switch register 2
RI_IOSR3  0x543b I/O switch register 3
RI_IOGCR  0x543c I/O group control register
RI_ASCR1  0x543d Analog switch register 1
RI_ASCR2  0x543e Analog switch register 2
RI_RCR    0x543f Resistor control register

;/* Comparators (COMP) */
;/*****************************************************************/
COMP_CSR1 0x5440 Comparator control and status register 1
COMP_CSR2 0x5441 Comparator control and status register 2
COMP_CSR3 0x5442 Comparator control and status register 3
COMP_CSR4 0x5443 Comparator control and status register 4
COMP_CSR5 0x5444 Comparator control and status register 5

;/* Global configuration register (CFG) */
;/*****************************************************************/
CFG_GCR 0x7f60 CFG Global configuration register

;/* Interrupt Software Priority Registers (ITC) */
;/*****************************************************************/
ITC_SPR1 0x7f70 Interrupt Software priority register 1
ITC_SPR2 0x7f71 Interrupt Software priority register 2
ITC_SPR3 0x7f72 Interrupt Software priority register 3
ITC_SPR4 0x7f73 Interrupt Software priority register 4
ITC_SPR5 0x7f74 Interrupt Software priority register 5
ITC_SPR6 0x7f75 Interrupt Software priority register 6
ITC_SPR7 0x7f76 Interrupt Software priority register 7
ITC_SPR8 0x7f77 Interrupt Software priority register 8