Libero SoC 2024.1 designs - v1.0

Libero SoC 2024.1 designs - v1.0

1. Libero Scripted Designs Update for v2024.1
2. MIV_RV32 in the designs has been updated from: v3.1.100 to v3.1.200.
3. MIV_ESS in the designs has been updated from: v2.0.100 to v2.0.200.
4. FlashPro_Express_Projects have been updated to reflect the latest design changes
5. Readme files updated.

Libero SoC 2023.2 designs - v1.0

Libero SoC 2023.2 designs - v1.0

• Libero Scripted Designs Update for v2023.2
• MIV_RV32 in the designs has been updated from: v3.1.100 to v3.1.200.
• MIV_ESS in the designs has been updated from: v2.0.100 to v2.0.200.
• Updated Out-of-box example using the CoreTimer example for MIV_RV32. After programming the bitstream, software boots out of the box from the LSRAM.
• FlashPro_Express_Projects have been updated to reflect the latest design changes
• Readme files updated.

Libero SoC 2023.1 designs - v1.0

Updated to support Libero SoC v2023.1

• Notice added to Libero_Project and FlashPro_Express_Projects regarding the work around for the MTVEC issue for FreeRTOS and the Fast Interrupt issue in the latest release of the MIV_RV32. Please read the readme files in each of those folders to see if you are effected.

Features of this release:

• Updated .job files to v2023.1.
• Engineering Samples .job files not included.
• MIV_RV32 and support components update to latest release.
• Refactored TCL script library, updated for modularity, parameterization and input handling
  • New dynamic paths added, should allow for better performance on non-Windows based OS systems.
  • Design components are now downloaded dynamically for each design configuration
  • Removed glitches which may have been seen when adapting the designs for VHDL
  • Project folders for ES designs have been uniquified for traceability
  • Project folders for MIV_RV32, MIV_RV32IMAF and MIV_RV32IMA have been uniquified for clarity and traceability
• Improved TCL output messaging with regards to the design building and design flow progression
• An example software program has been added to LSRAM-based configurations. After programming the bitstream, software boots out of the box from the LSRAM.
• The clocking circuitry in all of the designs has been improved. A new 50MHz clock reference for the CCC has been added by replacing the RC Oscillator. Timing has been improved across the designs

Libero SoC 2022.2 designs - v1.0

Updated to support Libero SoC v2022.2
Features of this release:

Updated .job files to v2022.2
Removed Engineering Samples .job files
CFG1, CFG2 and CFG3 with the MIV_RV32 in it now have the MIV_ESS incorporated
The MIV_ESS tcl file was added to the shared components folder.

Libero SoC 2022.1 designs - v1.0

Updated to support Libero SoC v2022.1

Features of this release:

• A 3rd argument has been added to the scripts which could be passed in
  to specify the board's die type.
• Top level scripts for 'ES' die type targets have been merged with 'PS'
  die type scripts. A 3rd argument is now used to specify desired die type for
  building a design.
• Improved script execution log messaging
• 'ES' bitstream now supplied for DGC2 design config
• CoreAHBLite DirectCore updated from v5.5.105 to 5.6.105
• A missing connection was added in CFG designs for "FPGA_POR_ON" signal,
  between PF_INIT_MONITOR and CoreRESET_PF.
• Designs now auto-arrange SmartDesign layout after building
• New bitstreams/programming files that have been generated in Libero SoC v2022.1
• Readmes updated (including DGC2)

Libero SoC 2021.3 designs - v1.0

Updated to support Libero SoC v2021.3

Features of this release:

• DGC2: I2C Boot & Write design has been added
• Bootloader .elf program added for DGC2, with reference to Bare Metal source
• Wild card component version numbers for SgCores have been added in TCL
• MIV_RV32 CFG1 TCL design now has TCM enabled (32kB)
• SgCores updated with this release:
  • PF_INIT_MONITOR: from v2.0.204 to v2.0.205
• New programming files added for DGC2, MIV_RV32_L1_AHB_IMAF ES and MIV_RV32 CFG1 designs and
• Readmes updated and DGC2 readme added