Some video refactoring and cleanup.

C64-lite.qsf

@@ -366,8 +366,7 @@ set_global_assignment -name VHDL_FILE spram.vhd
 set_global_assignment -name VERILOG_FILE sdram.v
 set_global_assignment -name VERILOG_FILE cartridge.v
 set_global_assignment -name VHDL_FILE video_sync.vhd
-set_global_assignment -name VHDL_FILE video_vicII_656x_e.vhd
-set_global_assignment -name VHDL_FILE video_vicII_656x_a.vhd
+set_global_assignment -name VHDL_FILE video_vicII_656x.vhd
 set_global_assignment -name VHDL_FILE fpga64_rgbcolor.vhd
 set_global_assignment -name VHDL_FILE fpga64_keyboard.vhd
 set_global_assignment -name VHDL_FILE fpga64_bustiming.vhd

C64.qsf

@@ -365,8 +365,7 @@ set_global_assignment -name VHDL_FILE spram.vhd
 set_global_assignment -name VERILOG_FILE sdram.v
 set_global_assignment -name VERILOG_FILE cartridge.v
 set_global_assignment -name VHDL_FILE video_sync.vhd
-set_global_assignment -name VHDL_FILE video_vicII_656x_e.vhd
-set_global_assignment -name VHDL_FILE video_vicII_656x_a.vhd
+set_global_assignment -name VHDL_FILE video_vicII_656x.vhd
 set_global_assignment -name VHDL_FILE fpga64_rgbcolor.vhd
 set_global_assignment -name VHDL_FILE fpga64_keyboard.vhd
 set_global_assignment -name VHDL_FILE fpga64_bustiming.vhd

c64.vhd

@@ -457,9 +457,6 @@ end component opl;
 	signal clk32     : std_logic;
 	signal clk64     : std_logic;
 	signal clk_opl   : std_logic;
-	signal clkdiv    : std_logic_vector(9 downto 0);
-	signal ce_8      : std_logic;
-	signal ce_4      : std_logic;
 	signal hq2x160   : std_logic;
 
 	signal sysram_ce        : std_logic;
@@ -469,6 +466,7 @@ end component opl;
 
 	signal scandoubler : std_logic;
 	signal forced_scandoubler : std_logic;
+	signal clkdivpix : std_logic_vector(3 downto 0);
 	signal ce_pix    : std_logic;
 	signal r,g,b     : unsigned(7 downto 0);
 	signal hsync     : std_logic;
@@ -713,23 +711,6 @@ begin
 	c64rom_wr   <= ioctl_wr when (ioctl_index = 0) and (ioctl_addr(14) = '0') and (ioctl_download = '1') else '0';
 	c1541rom_wr <= ioctl_wr when (ioctl_index = 0) and (ioctl_addr(14) = '1') and (ioctl_download = '1') else '0';
 
-	process(clk32)
-	begin
-		if rising_edge(clk32) then
-			clkdiv <= std_logic_vector(unsigned(clkdiv)+1);
-			if(clkdiv(1 downto 0) = "00") then
-				ce_8 <= '1';
-			else
-				ce_8 <= '0';
-			end if;
-			if(clkdiv(2 downto 0) = "000") then
-				ce_4 <= '1';
-			else
-				ce_4 <= '0';
-			end if;
-		end if;
-	end process;
-
 	mainpll : pll
 	port map(
 		refclk   => CLK_50M,
@@ -892,7 +873,7 @@ begin
 		led => LED_USER
 	);
 
-	comp_sync : entity work.video_sync
+	sync : entity work.video_sync
 	port map
 	(
 		clk32 => clk32,
@@ -905,9 +886,6 @@ begin
 		vblank => vblank
 	);
 
-	ce_pix <= ce_4 when hq2x160='1' else ce_8;
-	scandoubler <= '1' when (status(10 downto 8)/="000" or forced_scandoubler='1') else '0';
-
 	process(clk32)
 	begin
 		if rising_edge(clk32) then
@@ -922,6 +900,10 @@ begin
 		end if;
 	end process;
 
+	clkdivpix <= clkdivpix+"1" when rising_edge(clk64);
+	ce_pix <= (not clkdivpix(3) or not hq2x160) and not clkdivpix(2) and not clkdivpix(1) and not clkdivpix(0);
+
+	scandoubler <= '1' when (status(10 downto 8)/="000" or forced_scandoubler='1') else '0';
 	scanlines <= "01" when status(10 downto 8) = "011" else "10" when status(10 downto 8) = "100" else "00";
 
 	vmixer : video_mixer

sys/scandoubler.v

@@ -52,7 +52,7 @@ module scandoubler #(parameter LENGTH, parameter HALF_DEPTH)
 
 localparam DWIDTH = HALF_DEPTH ? 3 : 7;
 
-assign vs_out = vs_in;
+assign vs_out = vso[3];
 assign ce_pix_out = ce_x4;
 
 //Compensate picture shift after HQ2x
@@ -117,6 +117,7 @@ reg [DWIDTH:0] r_d;
 reg [DWIDTH:0] g_d;
 reg [DWIDTH:0] b_d;
 
+reg [3:0] vso;
 
 always @(posedge clk_sys) begin
 
@@ -143,6 +144,7 @@ always @(posedge clk_sys) begin
 
 		// falling edge of hsync indicates start of line
 		if(hs && !hs_in) begin
+			vso <= (vso<<1) | vs_in;
 			hs_max <= {hcnt,1'b1};
 			hcnt <= 0;
 		end else begin

sys/video_mixer.sv

@@ -160,7 +160,7 @@ always @(posedge clk_sys) begin
 	VGA_HS <= hs;
 
 	old_hde <= hde;
-	if(~old_hde && hde && vde) VGA_DE <= 1;
+	if(~old_hde && hde) VGA_DE <= vde;
 	if(old_hde && ~hde) VGA_DE <= 0;
 end
 

video_vicII_656x_a.vhd → video_vicII_656x.vhd

@@ -14,13 +14,63 @@
 -- -----------------------------------------------------------------------
 -- Dar 08/03/2014 : shift hsync to sprite #3
 -- -----------------------------------------------------------------------
-
+
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.numeric_std.ALL;
-
--- -----------------------------------------------------------------------
-
+
+entity video_vicii_656x is
+	generic (
+		registeredAddress : boolean;
+		emulateRefresh : boolean := false;
+		emulateLightpen : boolean := false;
+		emulateGraphics : boolean := true
+	);
+	port (
+		clk: in std_logic;
+		-- phi = 0 is VIC cycle
+		-- phi = 1 is CPU cycle (only used by VIC when BA is low)
+		phi : in std_logic;
+		enaData : in std_logic;
+		enaPixel : in std_logic;
+
+		baSync : in std_logic;
+		ba: out std_logic;
+
+		mode6569 : in std_logic; -- PAL 63 cycles and 312 lines
+		mode6567old : in std_logic; -- old NTSC 64 cycles and 262 line
+		mode6567R8 : in std_logic; -- new NTSC 65 cycles and 263 line
+		mode6572 : in std_logic; -- PAL-N 65 cycles and 312 lines
+
+		reset : in std_logic;
+		cs : in std_logic;
+		we : in std_logic;
+		rd : in std_logic;
+		lp_n : in std_logic;
+
+		aRegisters: in unsigned(5 downto 0);
+		diRegisters: in unsigned(7 downto 0);
+
+		di: in unsigned(7 downto 0);
+		diColor: in unsigned(3 downto 0);
+		do: out unsigned(7 downto 0);
+
+		vicAddr: out unsigned(13 downto 0);
+		irq_n: out std_logic;
+
+		-- Video output
+		hSync : out std_logic;
+		vSync : out std_logic;
+		colorIndex : out unsigned(3 downto 0);
+
+		-- Debug outputs
+		debugX : out unsigned(9 downto 0);
+		debugY : out unsigned(8 downto 0);
+		vicRefresh : out std_logic;
+		addrValid : out std_logic
+	);
+end entity;
+
 architecture rtl of video_vicii_656x is
 	type vicCycles is (
 		cycleRefresh1, cycleRefresh2, cycleRefresh3, cycleRefresh4, cycleRefresh5,