Merge pull request #2 from S0urceror/master

MultiComp works now with Images and UART

.gitignore

@@ -0,0 +1,6 @@
+db/*
+incremental_db/*
+output_files/*
+.DS_Store
+**/pll_sim/*
+**/*.bak

Components/INTERNALRAM/InternalRam64K.qip

@@ -1,4 +1,5 @@
 set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT"
-set_global_assignment -name IP_TOOL_VERSION "13.0"
+set_global_assignment -name IP_TOOL_VERSION "17.0"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
 set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "InternalRam64K.vhd"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "InternalRam64K.cmp"]

Components/INTERNALRAM/InternalRam64K.vhd

@@ -4,7 +4,7 @@
 -- MODULE: altsyncram 
 
 -- ============================================================
--- File Name: InternalRam4K.vhd
+-- File Name: InternalRam64K.vhd
 -- Megafunction Name(s):
 -- 			altsyncram
 --
@@ -14,32 +14,33 @@
 -- ************************************************************
 -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 --
--- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
+-- 17.0.0 Build 595 04/25/2017 SJ Lite Edition
 -- ************************************************************
 
 
---Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
+--Copyright (C) 2017  Intel Corporation. All rights reserved.
+--Your use of Intel Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 
 --(including device programming or simulation files), and any 
 --associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
+--to the terms and conditions of the Intel Program License 
+--Subscription Agreement, the Intel Quartus Prime License Agreement,
+--the Intel MegaCore Function License Agreement, or other 
+--applicable license agreement, including, without limitation, 
+--that your use is for the sole purpose of programming logic 
+--devices manufactured by Intel and sold by Intel or its 
+--authorized distributors.  Please refer to the applicable 
+--agreement for further details.
 
 
 LIBRARY ieee;
 USE ieee.std_logic_1164.all;
 
 LIBRARY altera_mf;
-USE altera_mf.all;
+USE altera_mf.altera_mf_components.all;
 
-ENTITY internalram64k IS
+ENTITY InternalRam64K IS
 	PORT
 	(
 		address		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
@@ -55,48 +56,22 @@ ARCHITECTURE SYN OF internalram64k IS
 
 	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (7 DOWNTO 0);
 
-
-
-	COMPONENT altsyncram
-	GENERIC (
-		clock_enable_input_a		: STRING;
-		clock_enable_output_a		: STRING;
-		intended_device_family		: STRING;
-		lpm_hint		: STRING;
-		lpm_type		: STRING;
-		numwords_a		: NATURAL;
-		operation_mode		: STRING;
-		outdata_aclr_a		: STRING;
-		outdata_reg_a		: STRING;
-		power_up_uninitialized		: STRING;
-		widthad_a		: NATURAL;
-		width_a		: NATURAL;
-		width_byteena_a		: NATURAL
-	);
-	PORT (
-			address_a	: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
-			clock0	: IN STD_LOGIC ;
-			data_a	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-			wren_a	: IN STD_LOGIC ;
-			q_a	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
-	);
-	END COMPONENT;
-
 BEGIN
 	q    <= sub_wire0(7 DOWNTO 0);
 
 	altsyncram_component : altsyncram
 	GENERIC MAP (
 		clock_enable_input_a => "BYPASS",
 		clock_enable_output_a => "BYPASS",
-		intended_device_family => "Cyclone",
+		intended_device_family => "Cyclone V",
 		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
 		lpm_type => "altsyncram",
 		numwords_a => 65536,
 		operation_mode => "SINGLE_PORT",
 		outdata_aclr_a => "NONE",
 		outdata_reg_a => "UNREGISTERED",
 		power_up_uninitialized => "FALSE",
+		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
 		widthad_a => 16,
 		width_a => 8,
 		width_byteena_a => 1
@@ -131,7 +106,7 @@ END SYN;
 -- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
 -- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
 -- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
 -- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
 -- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
 -- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
@@ -146,29 +121,30 @@ END SYN;
 -- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
 -- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
 -- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
--- Retrieval info: PRIVATE: WidthAddr NUMERIC "15"
+-- Retrieval info: PRIVATE: WidthAddr NUMERIC "16"
 -- Retrieval info: PRIVATE: WidthData NUMERIC "8"
 -- Retrieval info: PRIVATE: rden NUMERIC "0"
 -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
 -- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
 -- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
--- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
 -- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
 -- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
 -- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "65536"
 -- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
 -- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
 -- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
 -- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
--- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "15"
+-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "16"
 -- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
 -- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
--- Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
+-- Retrieval info: USED_PORT: address 0 0 16 0 INPUT NODEFVAL "address[15..0]"
 -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
 -- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
 -- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
 -- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
--- Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
+-- Retrieval info: CONNECT: @address_a 0 0 16 0 address 0 0 16 0
 -- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
 -- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
 -- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0