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Merge pull request #68 from MiSTer-devel/main
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MiSTer-devel updates
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spark2k06 committed Oct 24, 2022
2 parents 0c3e331 + 7c5a452 commit 07eadde
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78 changes: 40 additions & 38 deletions PCXT.sv
Original file line number Diff line number Diff line change
Expand Up @@ -210,21 +210,29 @@ module emu

localparam CONF_STR = {
"PCXT;;",
"S0,IMGIMAVFD,Floppy A:;",
"S1,IMGIMAVFD,Floppy B:;",
"OJK,Write Protect,None,A:,B:,A: & B:;",
"-;",
"O3,Model,IBM PCXT,Tandy 1000;",
"OHI,CPU Speed,4.77MHz,7.16MHz,14.318MHz;",
"S2,IMG,HDD Image:;",
"-;",
"O7,Splash Screen,Yes,No;",
"OHI,CPU Speed,4.77MHz,7.16MHz,14.318MHz;",
"-;",
"P1,FDD & HDD;",
"P1S0,IMGIMAVFD,Floppy A:;",
"P1S1,IMGIMAVFD,Floppy B:;",
"P1OJK,Write Protect,None,A:,B:,A: & B:;",
"P1,System & BIOS;",
"P1-;",
"P1O3,Model,IBM PCXT,Tandy 1000;",
"P1-;",
"P1S2,IMG,HDD Image:;",
"P1OLM,HDD COM Speed,115200,230400,460800,921600;",
"P1-;",
"P1OLM,Speed,115200,230400,460800,921600;",
"P1O7,Boot Splash Screen,Yes,No;",
"P1-;",
"P1FC0,ROM,PCXT BIOS:;",
"P1FC1,ROM,Tandy BIOS:;",
"P1-;",
"P1FC2,ROM,EC00 BIOS:;",
"P1-;",
"P1OUV,BIOS Writable,None,EC00,PCXT/Tandy,All;",
"P1-;",
"P2,Audio & Video;",
"P2-;",
"P2OA,Adlib,On,Invisible;",
Expand All @@ -239,6 +247,7 @@ module emu
"P2O4,Video Output,CGA/Tandy,MDA;",
"P2o8,Composite video,Off,On;",
"P2OEG,Display,Full Color,Green,Amber,B&W,Red,Blue,Fuchsia,Purple;",
"P2-;",
"P3,Hardware;",
"P3-;",
"P3OB,Lo-tech 2MB EMS,Enabled,Disabled;",
Expand All @@ -248,25 +257,17 @@ module emu
"P3OPQ,Joystick 2, Analog, Digital, Disabled;",
"P3OR,Sync Joy to CPU Speed,No,Yes;",
"P3OS,Swap Joysticks,No,Yes;",
"P3-;",
"-;",
"P4,BIOS;",
"P4-;",
"P4FC0,ROM,PCXT BIOS:;",
"P4FC1,ROM,Tandy BIOS:;",
"P4-;",
"P4FC2,ROM,EC00 BIOS:;",
"P4-;",
"P4OUV,BIOS Writable,None,EC00,PCXT/Tandy,All;",
"P3-;",
"-;",
"R0,Reset & apply model;",
"R0,Reset & apply settings;",
"J,Fire 1, Fire 2;",
"V,v",`BUILD_DATE
};

wire forced_scandoubler;
wire [1:0] buttons;
wire [63:0] status;
wire [7:0] xtctl;

//VHD
// wire[ 0:0] usdRd = { vsdRd };
Expand Down Expand Up @@ -300,17 +301,17 @@ module emu
reg ioctl_wait;

wire [21:0] gamma_bus;
wire adlibhide = status[10];
wire adlibhide = status[10] | xtctl[4];

wire [31:0] joy0, joy1;
wire [15:0] joya0, joya1;
wire [4:0] joy_opts = status[27:23];

wire composite = status[40];
wire composite = status[40] | xtctl[0];
wire [1:0] scale = status[2:1];
wire mda_mode = status[4];
wire mda_mode = status[4] | xtctl[5];
wire [2:0] screen_mode = status[16:14];
wire border = status[29];
wire border = status[29] | xtctl[1];


hps_io #(.CONF_STR(CONF_STR), .PS2DIV(2000), .PS2WE(1), .WIDE(1)) hps_io
Expand Down Expand Up @@ -338,7 +339,7 @@ module emu
// .img_mounted (usdImgMtd),
// .img_size (usdImgSz),

.ps2_kbd_clk_in (ps2_kbd_clk_out),
.ps2_kbd_clk_in (ps2_kbd_clk_out),
.ps2_kbd_data_in (ps2_kbd_data_out),
.ps2_kbd_clk_out (ps2_kbd_clk_in),
.ps2_kbd_data_out (ps2_kbd_data_in),
Expand Down Expand Up @@ -432,18 +433,18 @@ module emu
HBlank_del <= {HBlank_del[13], HBlank_del[12], HBlank_del[11], HBlank_del[10], HBlank_del[9],
HBlank_del[8], HBlank_del[7], HBlank_del[6], HBlank_del[5], HBlank_del[4],
HBlank_del[3], HBlank_del[2], HBlank_del[1], HBlank_del[0], HBlank};
clk_14_318 <= ~clk_14_318; // 14.318Mhz
clk_14_318 <= ~clk_14_318; // 14.318Mhz
ce_pixel_cga <= clk_14_318; //if outside always block appears an overscan column in CGA mode
end

always @(posedge clk_14_318)
clk_7_16 <= ~clk_7_16; // 7.16Mhz
clk_7_16 <= ~clk_7_16; // 7.16Mhz

clk_div3 clk_normal // 4.77MHz
(
.clk(clk_14_318),
.clk_out(clk_4_77)
);
clk_div3 clk_normal // 4.77MHz
(
.clk(clk_14_318),
.clk_out(clk_4_77)
);

always @(posedge clk_4_77)
peripheral_clock <= ~peripheral_clock; // 2.385Mhz
Expand All @@ -466,8 +467,8 @@ module emu
end
else if (biu_done)
begin
turbo_mode <= (status[18:17] == 2'b01 || status[18:17] == 2'b10);
clk_select <= status[18:17];
turbo_mode <= xtctl[3:2] == 2'b00 ? (status[18:17] == 2'b01 || status[18:17] == 2'b10) : (xtctl[3:2] == 2'b10 || xtctl[3:2] == 2'b11);
clk_select <= xtctl[3:2] == 2'b00 ? status[18:17] : xtctl[3:2] - 2'b01;
end
else
begin
Expand Down Expand Up @@ -796,7 +797,7 @@ module emu
bios_protect_flag <= 1'b1;
bios_access_request <= 1'b0;
bios_access_address <= 20'hFFFFF;
bios_write_data <= 8'hFFFF;
bios_write_data <= 16'hFFFF;
bios_write_n <= 1'b1;
bios_write_wait_cnt <= 'h0;
bios_write_byte_cnt <= 1'h0;
Expand Down Expand Up @@ -915,10 +916,10 @@ module emu
CHIPSET u_CHIPSET
(
.clock (clk_chipset),
.cpu_clock (clk_cpu),
.cpu_clock (clk_cpu),
.clk_sys (clk_chipset),
.peripheral_clock (pclk),
.turbo_mode (status[18:17]),
.turbo_mode (xtctl[3:2] == 2'b00 ? status[18:17] : xtctl[3:2] - 2'b01),
.reset (reset_cpu),
.sdram_reset (reset_sdram),
.cpu_address (cpu_address),
Expand Down Expand Up @@ -1029,7 +1030,8 @@ module emu
.mgmt_read (mgmt_rd),
.clock_rate (cur_rate),
.floppy_wp (status[20:19]),
.fdd_request (mgmt_req[7:6])
.fdd_request (mgmt_req[7:6]),
.xtctl (xtctl)
);

wire [15:0] SDRAM_DQ_IN;
Expand Down
2 changes: 2 additions & 0 deletions README.md
Original file line number Diff line number Diff line change
Expand Up @@ -58,6 +58,8 @@ Other Open Source ROMs are available in the same folder:
* `pcxt_micro8088.rom`: This ROM already has the XTIDE BIOS embedded at address F000h. ([Source Code](https://github.com/skiselev/8088_bios))
* `ide_xtl.rom`: This ROM corresponds to the XTIDE BIOS, it must be maintained for some scripts to work, it can also be upgraded to a newer version. ([Source Code](https://www.xtideuniversalbios.org/))

Note: Not all ROMs work with MDA video: (IBM5160, Yuko ST and pcxt31 works), (Tandy, micro8088, full XTIDE BIOS do not work).

## Mounting the FDD image

The floppy disk image size must be compatible with the BIOS, for example:
Expand Down
19 changes: 19 additions & 0 deletions SW/XTCTL/README.txt
Original file line number Diff line number Diff line change
@@ -0,0 +1,19 @@
USAGE:

xtctl.exe [menu] [composite border adliboff mda 4Mhz/7Mhz/14Mhz]

Composite video simulated and visible bordes would be:

xtctl composite border

Adlib hidden and 14Mhz would be:

xtctl adliboff 14

This would restore normal operation:

sysctl menu

It is not cumulative, any new execution of the tool resets the status beforehand, all options that are not selected will take into account the menu configuration.

A warm restart (CTRL+ALT+SUPR) does not restore the initial state, but a cold restart does (restart from the menu).
80 changes: 80 additions & 0 deletions SW/XTCTL/XTCTL.C
Original file line number Diff line number Diff line change
@@ -0,0 +1,80 @@
#include <stdio.h>
#include <conio.h>
#include <string.h>

#define COMP 0x01
#define BORDER 0x02
#define ADLIBOFF 0x10
#define MDA 0x20

static int _argc;
static char **_argv;

int chk_arg_opt(char * option)
{
int index;
for(index = 1; index < _argc; index++)
if(strcmpi(_argv[index], option) == 0)
return index;
return 0;
}

int main(int argc, char **argv)
{
unsigned char arg = 0;
char * argv0;
char * bs;

if(argc < 2)
{
printf("XTCTL 1.0\n");
printf("USAGE:\n");
bs = strrchr(argv[0], '\\');
if(bs == NULL)
argv0 = argv[0];
else
argv0 = ++bs;
printf("%s [menu] [composite border adliboff mda 4Mhz/7Mhz/14Mhz]\n", argv0);
return -1;
}

_argc = argc;
_argv = argv;

if (chk_arg_opt("menu"))
arg = 0;
else
{
if (chk_arg_opt("composite"))
arg |= COMP;

if (chk_arg_opt("border"))
arg |= BORDER;

if (chk_arg_opt("adliboff"))
arg |= ADLIBOFF;

if (chk_arg_opt("mda"))
arg |= MDA;

if (chk_arg_opt("4Mhz") || chk_arg_opt("4"))
{
arg |= 1 << 2;
arg &= ~(1 << 3);
}
else if (chk_arg_opt("7Mhz") || chk_arg_opt("7"))
{
arg &= ~(1 << 2);
arg |= 1 << 3;
}
else if (chk_arg_opt("14Mhz") || chk_arg_opt("14"))
{
arg |= 1 << 2;
arg |= 1 << 3;
}
}

outp(0x8888, arg);

return 0;
}
9 changes: 9 additions & 0 deletions SW/XTCTL/makefile
Original file line number Diff line number Diff line change
@@ -0,0 +1,9 @@
all: xtctl.exe

sysctl.exe: xtctl.c
wcl -q -y -4 -s -d0 -lr -ms -we -wx -k1024 -os xtctl.c -fe=xtctl.exe

clean:
if exist *.obj del *.obj
if exist *.map del *.map
if exist *.bak del *.bak
2 changes: 1 addition & 1 deletion SW/splash.txt
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
(_()((_|(_|_)) (_(_())/((_|()\ (_)) )\_____((_)(_(_())
| \/ |(_) __||_ _(_)) ((_) | _ ((/ __\ \/ /|_ _|
| |\/| || \__ \ | | / -_)| '_| | _/| (__ > < | |
|_| |_||_|___/ |_| \___||_| |_| \___/_/\_\ |_| 11/10/2022
|_| |_||_|___/ |_| \___||_| |_| \___/_/\_\ |_| 24/10/2022


Port by @spark2k06
Expand Down
Binary file added hdd/XTCTL.EXE
Binary file not shown.
Binary file added releases/PCXT_20221024.rbf
Binary file not shown.
3 changes: 1 addition & 2 deletions rtl/8088/8088.qip
Original file line number Diff line number Diff line change
@@ -1,5 +1,4 @@
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) mcl86_eu_core.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) i8088.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) eu_rom.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) biu_min.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) biu_max.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) biu_max.v ]
7 changes: 5 additions & 2 deletions rtl/KFPC-XT/HDL/Chipset.sv
Original file line number Diff line number Diff line change
Expand Up @@ -137,7 +137,9 @@ module CHIPSET (
input logic [15:0] mgmt_writedata,
input logic [27:0] clock_rate,
input logic [1:0] floppy_wp,
output logic [1:0] fdd_request
output logic [1:0] fdd_request,
// XTCTL DATA
output logic [7:0] xtctl
);

logic dma_ready;
Expand Down Expand Up @@ -342,7 +344,8 @@ module CHIPSET (
.fdd_request (fdd_request),
.fdd_dma_req (fdd_dma_req),
.fdd_dma_ack (~dma_acknowledge_n[2]),
.terminal_count (terminal_count_n)
.terminal_count (terminal_count_n),
.xtctl (xtctl)
);

RAM u_RAM
Expand Down

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