Turbosound: fix PSG prescaler, some tweaks.

MiSTer-devel · Aug 18, 2018 · 49a0e8b · 49a0e8b
1 parent a4cc28a
commit 49a0e8b
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Showing 3 changed files with 34 additions and 35 deletions.
diff --git a/jt12/jt12_clksync.v b/jt12/jt12_clksync.v
@@ -68,7 +68,7 @@ always @(negedge syn_clk or posedge rst)
 reg		cpu_busy;
 wire		cpu_flag_B, cpu_flag_A;
 
-assign 	cpu_dout = { cpu_busy, 5'h0, cpu_flag_B, cpu_flag_A };
+assign 	cpu_dout = cpu_cs_n ? 8'hFF : { cpu_busy, 5'h0, cpu_flag_B, cpu_flag_A };
 
 wire		write_raw = !cpu_cs_n && !cpu_wr_n;
 

diff --git a/ym2149.sv b/ym2149.sv
@@ -79,7 +79,7 @@ assign     IOB_out = ymreg[15];
 
 reg        ena_div;
 reg        ena_div_noise;
-reg [3:0]  addr;
+reg [7:0]  addr;
 reg [7:0]  ymreg[16];
 reg        env_ena;
 reg [4:0]  env_vol;
@@ -106,24 +106,27 @@ wire [7:0] volTableYm[32] =
 assign DO = dout;
 reg [7:0] dout;
 always_comb begin
-	case(addr)
-		 0: dout = ymreg[0];
-		 1: dout = {4'b0000, ymreg[1][3:0]};
-		 2: dout = ymreg[2];
-		 3: dout = {4'b0000, ymreg[3][3:0]};
-		 4: dout = ymreg[4];
-		 5: dout = {4'b0000, ymreg[5][3:0]};
-		 6: dout = {3'b000,  ymreg[6][4:0]};
-		 7: dout = ymreg[7];
-		 8: dout = {3'b000,  ymreg[8][4:0]};
-		 9: dout = {3'b000,  ymreg[9][4:0]};
-		10: dout = {3'b000,  ymreg[10][4:0]};
-		11: dout = ymreg[11];
-		12: dout = ymreg[12];
-		13: dout = {4'b0000, ymreg[13][3:0]};
-		14: dout = (ymreg[7][6] ? ymreg[14] : IOA_in);
-		15: dout = (ymreg[7][7] ? ymreg[15] : IOB_in);
-	endcase
+	if(addr[7:4]) dout <= 8'hFF;
+	else begin
+		case(addr[3:0])
+			 0: dout = ymreg[0];
+			 1: dout = ymreg[1][3:0];
+			 2: dout = ymreg[2];
+			 3: dout = ymreg[3][3:0];
+			 4: dout = ymreg[4];
+			 5: dout = ymreg[5][3:0];
+			 6: dout = ymreg[6][4:0];
+			 7: dout = ymreg[7];
+			 8: dout = ymreg[8][4:0];
+			 9: dout = ymreg[9][4:0];
+			10: dout = ymreg[10][4:0];
+			11: dout = ymreg[11];
+			12: dout = ymreg[12];
+			13: dout = ymreg[13][3:0];
+			14: dout = (ymreg[7][6] ? ymreg[14] : IOA_in);
+			15: dout = (ymreg[7][7] ? ymreg[15] : IOB_in);
+		endcase
+	end
 end
 
 //  p_divider
@@ -279,9 +282,9 @@ always @(posedge CLK) begin
 	end else begin
 		old_BDIR <= BDIR;
 		if(~old_BDIR & BDIR) begin
-			if(BC) addr <= DI[3:0];
-			else begin
-				ymreg[addr] <= DI;
+			if(BC) addr <= DI;
+			else if(!addr[7:4])begin
+				ymreg[addr[3:0]] <= DI;
 				env_reset <= (addr == 13);
 			end
 		end

diff --git a/ym2203.sv b/ym2203.sv
@@ -25,7 +25,7 @@ module ym2203
 	input         CE_CPU,    // CPU Clock enable
 	input         CE_YM,     // YM2203 Master Clock enable x2 (due to YM2612 model!)
 
-	input         A0,        // 0 - register number, 1 - data
+	input         A0,        // 0 - register number/read FM, 1 - data/read PSG
 	input         WE,        // 0 - read , 1 - write
 	input   [7:0] DI,        // Data In
 	output  [7:0] DO,        // Data Out
@@ -41,13 +41,10 @@ module ym2203
 
 reg [7:0] ymreg;
 reg [1:0] pres;
-reg       psg_ena;
 
 always @(posedge CLK) begin
-	if(RESET) begin
-		pres    <= 3;
-		psg_ena <= 1;
-	end
+
+	if(RESET) pres <= 2;
 	else if(CE_CPU & WE) begin
 		if(FM_ENA) begin
 			if(~A0) ymreg  <= DI;
@@ -59,14 +56,13 @@ always @(posedge CLK) begin
 				endcase
 			end
 		end
-		if(~A0) psg_ena <= (~|DI[7:4]) | (~FM_ENA);
 	end
 end
 
-wire [2:0] opn_tbl[0:3] = '{1,1,5,2};
+wire [2:0] opn_tbl[4] = '{1,1,5,2};
 wire [2:0] opn_pres = opn_tbl[pres];
 
-wire [2:0] psg_tbl[0:3] = '{1,1,7,3};
+wire [2:0] psg_tbl[4] = '{0,0,3,1};
 wire [2:0] psg_pres = psg_tbl[pres];
 
 reg ce_psg_pre, ce_opn_pre;
@@ -97,7 +93,7 @@ ym2149 ym2149
 	.CLK(CLK),
 	.CE(ce_psg),
 	.RESET(RESET),
-	.BDIR(WE & (~A0 | psg_ena)),
+	.BDIR(WE),
 	.BC(~A0),
 	.DI(DI),
 	.DO(psg_dout),
@@ -119,8 +115,8 @@ jt12 jt12
 	.cpu_din(DI),
 	.cpu_dout(opn_dout),
 	.cpu_addr({1'b0,A0}),
-	.cpu_cs_n(1'b0),
-	.cpu_wr_n(~(WE & FM_ENA)),
+	.cpu_cs_n(~FM_ENA),
+	.cpu_wr_n(~WE),
 
 	.syn_clk(CLK & ce_opn),
 	.cpu_limiter_en(1'b1),