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Add auto region selection (latest unstable Main is required)
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@srg320 @theypsilon
srg320 authored and theypsilon committed Mar 4, 2024
2 parents 8783ce3 + cc8ac31 commit 7cfb023
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Showing 5 changed files with 654 additions and 549 deletions.
30 changes: 26 additions & 4 deletions Saturn.sv
View file
Expand Up @@ -247,7 +247,7 @@ module emu
"FS3,BIN,Load cartridge;",
"-;",
"OLN,Cartridge,None,ROM 2M,DRAM 1M,DRAM 4M;",
"o13,Region,Japan,Taiwan,USA,Brazil,Korea,Asia,Europe;",
"o13,Region,Japan,Taiwan,USA,Brazil,Korea,Asia,Europe,Auto;",
"-;",
"D0RO,Load Backup RAM;",
"D0RP,Save Backup RAM;",
Expand Down Expand Up @@ -418,6 +418,8 @@ module emu
wire cart_download = ioctl_download & (ioctl_index[5:2] == 4'b0000 && ioctl_index[1:0] == 2'h3);
wire save_download = ioctl_download & (ioctl_index[5:2] == 4'b0001);
wire cdd_download = ioctl_download & (ioctl_index[5:2] == 4'b0010);
wire cdboot_download = ioctl_download & (ioctl_index[5:2] == 4'b0011);


reg osd_btn = 0;
// always @(posedge clk_sys) begin
Expand Down Expand Up @@ -515,7 +517,6 @@ module emu
end
end


wire reset = RESET | status[0] | buttons[1];

reg rst_ram = 0;
Expand All @@ -527,7 +528,25 @@ module emu
end

wire rst_sys = reset | download | rst_ram;


//region select
reg [7:0] cd_area_symbol;
always @(posedge clk_sys) begin
if (cdboot_download && ioctl_wr) begin
case (ioctl_addr[7:0])
8'h40: cd_area_symbol <= ioctl_data[7:0];
endcase
end
end
wire [3:0] cd_area_code = cd_area_symbol == "J" ? 4'h1 :
cd_area_symbol == "T" ? 4'h2 :
cd_area_symbol == "U" ? 4'h4 :
cd_area_symbol == "B" ? 4'h5 :
cd_area_symbol == "K" ? 4'h6 :
cd_area_symbol == "A" ? 4'hA :
cd_area_symbol == "E" ? 4'hC :
cd_area_symbol == "L" ? 4'hD :
4'h1;

wire [3:0] area_code = status[35:33] == 3'd0 ? 4'h1 : //Japan area
status[35:33] == 3'd1 ? 4'h2 : //Asia NTSC area
Expand All @@ -536,7 +555,8 @@ module emu
status[35:33] == 3'd4 ? 4'h6 : //Korea area
status[35:33] == 3'd5 ? 4'hA : //Asia PAL area
status[35:33] == 3'd6 ? 4'hC : //Europe PAL area
4'h3; //Reserved
cd_area_code; //Auto

wire [15:0] joy1 = {~joystick_0[0],~joystick_0[1],~joystick_0[2],~joystick_0[3],~joystick_0[7],~joystick_0[4],~joystick_0[6],~joystick_0[5],
~joystick_0[8],~joystick_0[9],~joystick_0[10],~joystick_0[11],~joystick_0[12],3'b111};
wire [15:0] joy2 = {~joystick_1[0],~joystick_1[1],~joystick_1[2],~joystick_1[3],~joystick_1[7],~joystick_1[4],~joystick_1[6],~joystick_1[5],
Expand Down Expand Up @@ -1273,6 +1293,8 @@ module emu
vdp1_state <= 2'd0;
end
end

default:;
endcase
end
end
Expand Down
108 changes: 72 additions & 36 deletions rtl/Saturn/SCSP/SCSP.sv
View file
Expand Up @@ -354,16 +354,20 @@ module SCSP (

bit [15: 0] SAO; //Sample offset integer
bit SADIR;//Sample address direction
bit SALOOP;//Sample address loop state
always @(posedge CLK or negedge RST_N) begin
bit [15: 0] SOUSX;
bit [15: 0] SOUSY;
bit [15: 0] CUR_SO;
bit CUR_SADIR;
bit CUR_SALOOP;
bit [15: 0] CALC_SO;
bit CALC_SO_OVF;
bit [15: 0] MOD_SO;
bit [15: 0] DELTA;
bit [15: 0] NEW_SAO;
bit NEW_SADIR;
bit NEW_SALOOP;

if (!RST_N) begin
// synopsys translate_off
Expand All @@ -381,94 +385,126 @@ module SCSP (
endcase
end

{CUR_SADIR,CUR_SO} = SO_RAM_Q;
{CUR_SALOOP,CUR_SADIR,CUR_SO} = SO_RAM_Q;

MOD_SO = CUR_SO + MDCalc(SOUSX, SOUSY, SCR4.MDL);

DELTA = {8'h00,OP2.PHASE_INT};
CALC_SO = !CUR_SADIR || SCR0.LPCTL <= 2'b01 ? CUR_SO + DELTA : CUR_SO - DELTA;
{CALC_SO_OVF,CALC_SO} = !CUR_SADIR || SCR0.LPCTL <= 2'b01 ? {1'b0,CUR_SO} + {1'b0,DELTA} : {1'b0,CUR_SO} - {1'b0,DELTA};

if (SLOT1_CE) begin
WD_READ <= 0;
ADP <= {SCR0.SAH,SA} + (!SCR0.PCM8B ? {3'b000,MOD_SO,1'b0} : {4'b0000,MOD_SO});

WD_READ <= 1;
OP3.LOOP_END <= 0;
if (OP2.RST) begin
{NEW_SADIR,NEW_SAO} = '0;
{NEW_SALOOP,NEW_SADIR,NEW_SAO} = '0;
WD_READ <= 0;
end else if (EST == EST_RELEASE && (EVOL == 10'h3FF || OP2.KON)) begin
{NEW_SADIR,NEW_SAO} = '0;
{NEW_SALOOP,NEW_SADIR,NEW_SAO} = '0;
WD_READ <= 0;
end else begin
{NEW_SADIR,NEW_SAO} = {CUR_SADIR,CALC_SO};
{NEW_SALOOP,NEW_SADIR,NEW_SAO} = {CUR_SALOOP,CUR_SADIR,CALC_SO};
case (SCR0.LPCTL)
2'b00: begin
if (CALC_SO > LEA - 1) begin
2'b00: begin //Loop off
if (CALC_SO >= LEA || CALC_SO_OVF) begin
NEW_SAO = '0;
OP3.LOOP_END <= 1;
WD_READ <= 0;
end
end
2'b01: begin
if (CALC_SO > LEA - 1) begin
NEW_SAO = LSA;
2'b01: begin //Normal loop
if (!CUR_SALOOP) begin
if (CALC_SO >= LSA || CALC_SO_OVF) begin
NEW_SALOOP = 1;
end
end else begin
if (CALC_SO >= LEA || CALC_SO_OVF) begin
NEW_SAO = CALC_SO - (LEA - LSA);
end
end
end
2'b10: begin
if (!CUR_SADIR) begin
if (CALC_SO > LEA - 1) begin
NEW_SAO = LEA;
2'b10: begin //Reverse loop
if (!CUR_SALOOP) begin
if (CALC_SO >= LEA || CALC_SO_OVF) begin
NEW_SALOOP = 1;
NEW_SADIR = 1;
end
end else begin
if (CALC_SO <= LSA) begin
NEW_SAO = LSA;
if (CALC_SO < LSA || CALC_SO_OVF) begin
NEW_SAO = LSA;//TODO
end
end
end
2'b11: begin

2'b11: begin //Alternative loop
if (!CUR_SALOOP) begin
if (CALC_SO >= LSA || CALC_SO_OVF) begin
NEW_SALOOP = 1;
NEW_SADIR = 0;
end
end else if (!CUR_SADIR) begin
if (CALC_SO >= LEA || CALC_SO_OVF) begin
NEW_SAO = CALC_SO - (LEA - LSA);
NEW_SADIR = 1;
end
end else begin
if (CALC_SO < LSA || CALC_SO_OVF) begin
NEW_SAO = LSA;//TODO
NEW_SADIR = 0;
end
end
end
endcase

WD_READ <= 1;
end
{SADIR,SAO} <= {NEW_SADIR,NEW_SAO};

MOD_SO = CUR_SO + MDCalc(SOUSX, SOUSY, SCR4.MDL);
ADP <= {SCR0.SAH,SA} + (!SCR0.PCM8B ? {3'b000,MOD_SO,1'b0} : {4'b0000,MOD_SO});
{SALOOP,SADIR,SAO} <= {NEW_SALOOP,NEW_SADIR,NEW_SAO};

OP3.SLOT <= OP2.SLOT;
OP3.RST <= OP2.RST;
OP3.KON <= OP2.KON;
OP3.KOFF <= OP2.KOFF;
OP3.PCM8B <= SCR0.PCM8B;
OP3.BASE_RATE <= OP2.BASE_RATE;
OP3.LOOP <= CUR_SALOOP;
OP3.SBCTL <= SCR0.SBCTL;
OP3.SSCTL <= SCR0.SSCTL;
OP3.EVOL <= EVOL;
OP3.EST <= EST;
end
end
end
bit [16:0] SO_RAM_Q;
SCSP_SO_RAM SO_RAM(CLK, OP3.SLOT, {SADIR,SAO}, SLOT1_CE, OP2.SLOT, SO_RAM_Q);
bit [17:0] SO_RAM_Q;
SCSP_SO_RAM SO_RAM(CLK, OP3.SLOT, {SALOOP,SADIR,SAO}, SLOT1_CE, OP2.SLOT, SO_RAM_Q);

//Operation 3:
always @(posedge CLK or negedge RST_N) begin
bit [15:0] TEMP;
bit [15: 0] WAVE;
bit [16: 0] NOISE;

if (!RST_N) begin
OP4 <= OP4_RESET;
// synopsys translate_off
NOISE <= 17'h00001;
// synopsys translate_on
end else if (!RES_N) begin
OP4 <= OP4_RESET;
NOISE <= 17'h00001;
end else begin
TEMP = !WD_READ ? 16'h0000 : !OP3.PCM8B ? MEM_WD : !ADP[0] ? {MEM_WD[15:8],8'h00} : {MEM_WD[7:0],8'h00};
WAVE = !WD_READ ? 16'h0000 : !OP3.PCM8B ? MEM_WD : !ADP[0] ? {MEM_WD[15:8],8'h00} : {MEM_WD[7:0],8'h00};

if (SLOT1_CE) begin
NOISE <= {NOISE[5]^NOISE[0],NOISE[16:1]};

OP4.SLOT <= OP3.SLOT;
OP4.RST <= OP3.RST;
OP4.KON <= OP3.KON;
OP4.KOFF <= OP3.KOFF;
OP4.LOOP <= OP3.LOOP;
OP4.LOOP_END <= OP3.LOOP_END;
OP4.BASE_RATE <= OP3.BASE_RATE;
OP4.EVOL <= OP3.EVOL;
OP4.EST <= OP3.EST;
OP4.WD <= SoundSel(TEMP,16'h0000,OP3.SBCTL,OP3.SSCTL);
OP4.WD <= SoundSel(WAVE,{NOISE[7:0],8'h00},OP3.SBCTL,OP3.SSCTL);
end
end
end
Expand Down Expand Up @@ -558,7 +594,7 @@ module SCSP (
end else begin
NEW_EVOL = 10'h000;
end
if (!VOL_CALC && !SCR2.LPSLNK) begin
if ((!VOL_CALC && !SCR2.LPSLNK) || (OP4.LOOP && SCR2.LPSLNK)) begin
NEW_EST = EST_DECAY1;
ENV_STEP_CNT <= '0;
`ifdef DEBUG
Expand Down Expand Up @@ -1970,10 +2006,10 @@ endmodule
module SCSP_SO_RAM (
input CLK,
input [ 4: 0] WRADDR,
input [16: 0] DATA,
input [17: 0] DATA,
input WREN,
input [ 4: 0] RDADDR,
output [16: 0] Q);
output [17: 0] Q);
//
//`ifdef DEBUG
//
Expand Down Expand Up @@ -2019,7 +2055,7 @@ module SCSP_SO_RAM (
//
//`else

wire [16:0] sub_wire0;
wire [17:0] sub_wire0;

altsyncram altsyncram_component (
.address_a (WRADDR),
Expand All @@ -2039,7 +2075,7 @@ module SCSP_SO_RAM (
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({17{1'b1}}),
.data_b ({18{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
Expand All @@ -2063,8 +2099,8 @@ module SCSP_SO_RAM (
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 5,
altsyncram_component.widthad_b = 5,
altsyncram_component.width_a = 17,
altsyncram_component.width_b = 17,
altsyncram_component.width_a = 18,
altsyncram_component.width_b = 18,
altsyncram_component.width_byteena_a = 1;

assign Q = sub_wire0;
Expand Down
6 changes: 4 additions & 2 deletions rtl/Saturn/SCSP/SCSP_pkg.sv
View file
Expand Up @@ -363,14 +363,15 @@ package SCSP_PKG;
bit KON; //
bit KOFF; //
bit [ 5: 0] BASE_RATE;
bit LOOP;//Loop processing
bit LOOP_END;//Loop processing end
bit PCM8B;//
bit [ 1: 0] SBCTL;
bit [ 1: 0] SSCTL;
bit [ 1: 0] EST;//Envelope state
bit [ 9: 0] EVOL;//Envelope volume
} OP3_t;
parameter OP3_t OP3_RESET = '{5'h00,1'b0,1'b0,1'b0,6'h00,1'b0,1'b0,2'h0,2'h0,2'h0,10'h000};
parameter OP3_t OP3_RESET = '{5'h00,1'b0,1'b0,1'b0,6'h00,1'b0,1'b0,1'b0,2'h0,2'h0,2'h0,10'h000};

typedef struct packed
{
Expand All @@ -379,12 +380,13 @@ package SCSP_PKG;
bit KON; //
bit KOFF; //
bit [ 5: 0] BASE_RATE;
bit LOOP;//Loop processing
bit LOOP_END;//Loop processing end
bit [ 1: 0] EST;//Envelope state
bit [ 9: 0] EVOL;//Envelope volume
bit [15: 0] WD;//Wave form data
} OP4_t;
parameter OP4_t OP4_RESET = '{5'h00,1'b0,1'b0,1'b0,6'h00,1'b0,2'h0,10'h000,16'h0000};
parameter OP4_t OP4_RESET = '{5'h00,1'b0,1'b0,1'b0,6'h00,1'b0,1'b0,2'h0,10'h000,16'h0000};

typedef struct packed
{
Expand Down

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