[slang] Introduce clock resolution support (SystemVerilog LRM 16.13/16.16 sections). #1852
Job | Run time |
---|---|
14m 41s | |
7m 30s | |
36m 27s | |
8m 30s | |
9m 27s | |
7m 41s | |
7m 56s | |
9m 7s | |
5m 9s | |
5m 15s | |
1h 51m 43s |
Job | Run time |
---|---|
14m 41s | |
7m 30s | |
36m 27s | |
8m 30s | |
9m 27s | |
7m 41s | |
7m 56s | |
9m 7s | |
5m 9s | |
5m 15s | |
1h 51m 43s |