[slang] Introduce clock resolution support (SystemVerilog LRM 16.13/16.16 sections). #1853
Job | Run time |
---|---|
7m 59s | |
36m 32s | |
13m 55s | |
8m 45s | |
8m 51s | |
7m 35s | |
7m 56s | |
6m 27s | |
10m 8s | |
8m 4s | |
1h 56m 12s |
Job | Run time |
---|---|
7m 59s | |
36m 32s | |
13m 55s | |
8m 45s | |
8m 51s | |
7m 35s | |
7m 56s | |
6m 27s | |
10m 8s | |
8m 4s | |
1h 56m 12s |