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Added Updated Y/C Module to the MiSTer Template
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@MikeS11
MikeS11 committed Oct 2, 2022
1 parent 10e2b6c commit ae73e54
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Showing 5 changed files with 329 additions and 17 deletions.
3 changes: 3 additions & 0 deletions mycore.qsf
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Expand Up @@ -67,6 +67,9 @@ set_global_assignment -name SEED 1
#use only 1MB per frame for scaler to free ~21MB DDR3 RAM
#set_global_assignment -name VERILOG_MACRO "MISTER_SMALL_VBUF=1"

# Enable YC / Composite output
#set_global_assignment -name VERILOG_MACRO "MISTER_ENABLE_YC=1"

source sys/sys.tcl
source sys/sys_analog.tcl
source files.qip
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32 changes: 32 additions & 0 deletions mycore.sv
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Expand Up @@ -53,6 +53,15 @@ module emu

input [11:0] HDMI_WIDTH,
input [11:0] HDMI_HEIGHT,

//Enable YC Output from the core
`ifdef MISTER_ENABLE_YC
output [39:0] CHROMA_PHASE_INC,
output [26:0] COLORBURST_RANGE,
output YC_EN,
output PALFLAG,
`endif

output HDMI_FREEZE,

`ifdef MISTER_FB
Expand Down Expand Up @@ -209,6 +218,7 @@ localparam CONF_STR = {
"O[122:121],Aspect ratio,Original,Full Screen,[ARC1],[ARC2];",
"O[2],TV Mode,NTSC,PAL;",
"O[4:3],Noise,White,Red,Green,Blue;",
// "O[22],Video Signal,RGBS/YPbPr,Y/C;",
"-;",
"P1,Test Page 1;",
"P1-;",
Expand Down Expand Up @@ -266,6 +276,28 @@ wire reset = RESET | status[0] | buttons[1];

//////////////////////////////////////////////////////////////////

// SET PAL and NTSC TIMING and pass through status bits. ** YC must be enabled in the qsf file **
`ifdef MISTER_ENABLE_YC
parameter NTSC_REF = 3.579545;
parameter PAL_REF = 4.43361875;
// Colorburst Lenth Calculation to send to Y/C Module, based on the CLK_VIDEO of the core
localparam [6:0] COLORBURST_START = (3.7 * (CLK_VIDEO_NTSC/NTSC_REF));
localparam [9:0] COLORBURST_NTSC_END = (9 * (CLK_VIDEO_NTSC/NTSC_REF)) + COLORBURST_START;
localparam [9:0] COLORBURST_PAL_END = (10 * (CLK_VIDEO_PAL/PAL_REF)) + COLORBURST_START;

// Parameters to be modifed
parameter CLK_VIDEO_NTSC = 42.3; // Must be filled E.g XX.X Hz - CLK_VIDEO
parameter CLK_VIDEO_PAL = 42.3; // Must be filled E.g XX.X Hz - CLK_VIDEO
localparam [39:0] NTSC_PHASE_INC = 40'd91625968981; // ((NTSC_REF**2^40) / CLK_VIDEO_NTSC) - SNES Example;
localparam [39:0] PAL_PHASE_INC = 40'd114532461227; // ((PAL_REF*2^40) / CLK_VIDEO_PAL)- SNES Example;

// Send Parameters to Y/C Module
assign CHROMA_PHASE_INC = PALFLAG ? PAL_PHASE_INC : NTSC_PHASE_INC;
assign YC_EN = status[2]; // Change the status to match your configuration
assign PALFLAG = status[2]; // if applicable, Change the status to match your configuration.
assign COLORBURST_RANGE = {COLORBURST_START, COLORBURST_NTSC_END, COLORBURST_PAL_END}; // Pass colorburst length
`endif

wire [1:0] col = status[4:3];

wire HBlank;
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1 change: 1 addition & 0 deletions sys/sys.qip
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Expand Up @@ -31,3 +31,4 @@ set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) d
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) sysmem.sv ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) sd_card.sv ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) hps_io.sv ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) yc_out.sv ]
82 changes: 65 additions & 17 deletions sys/sys_top.v
View file
Expand Up @@ -1152,6 +1152,9 @@ csync csync_hdmi(clk_hdmi, hdmi_hs_osd, hdmi_vs_osd, hdmi_cs_osd);

reg [23:0] dv_data;
reg dv_hs, dv_vs, dv_de;
wire [23:0] dv_data_osd;
wire dv_hs_osd, dv_vs_osd, dv_cs_osd;

always @(posedge clk_vid) begin
reg [23:0] dv_d1, dv_d2;
reg dv_de1, dv_de2, dv_hs1, dv_hs2, dv_vs1, dv_vs2;
Expand All @@ -1161,29 +1164,29 @@ always @(posedge clk_vid) begin
reg [3:0] hss;

if(ce_pix) begin
hss <= (hss << 1) | vga_hs_osd;
hss <= (hss << 1) | dv_hs_osd;

old_hs <= vga_hs_osd;
if(~old_hs && vga_hs_osd) begin
old_vs <= vga_vs_osd;
old_hs <= dv_hs_osd;
if(~old_hs && dv_hs_osd) begin
old_vs <= dv_vs_osd;
if(~&vcnt) vcnt <= vcnt + 1'd1;
if(~old_vs & vga_vs_osd) begin
if(~old_vs & dv_vs_osd) begin
if (vcnt != vcnt_ll || vcnt < vcnt_l) vsz <= vcnt;
vcnt_l <= vcnt;
vcnt_ll <= vcnt_l;
end
if(old_vs & ~vga_vs_osd) vcnt <= 0;
if(old_vs & ~dv_vs_osd) vcnt <= 0;

if(vcnt == 1) vde <= 1;
if(vcnt == vsz - 3) vde <= 0;
end

dv_de1 <= !{hss,vga_hs_osd} && vde;
dv_hs1 <= csync_en ? vga_cs_osd : vga_hs_osd;
dv_vs1 <= vga_vs_osd;
dv_de1 <= !{hss,dv_hs_osd} && vde;
dv_hs1 <= csync_en ? dv_cs_osd : dv_hs_osd;
dv_vs1 <= dv_vs_osd;
end

dv_d1 <= vga_data_osd;
dv_d1 <= dv_data_osd;
dv_d2 <= dv_d1;
dv_de2 <= dv_de1;
dv_hs2 <= dv_hs1;
Expand All @@ -1194,6 +1197,11 @@ always @(posedge clk_vid) begin
dv_hs <= dv_hs2;
dv_vs <= dv_vs2;
end
`ifdef MISTER_ENABLE_YC
assign {dv_data_osd, dv_hs_osd, dv_vs_osd, dv_cs_osd } = ~yc_en ? {vga_data_osd, vga_hs_osd, vga_vs_osd, vga_cs_osd } : {yc_o, yc_hs, yc_vs, yc_cs };
`else
assign {dv_data_osd, dv_hs_osd, dv_vs_osd, dv_cs_osd } = {vga_data_osd, vga_hs_osd, vga_vs_osd, vga_cs_osd };
`endif

wire hdmi_tx_clk;
`ifndef MISTER_DEBUG_NOHDMI
Expand Down Expand Up @@ -1330,31 +1338,60 @@ csync csync_vga(clk_vid, vga_hs_osd, vga_vs_osd, vga_cs_osd);
.csync_o(vgas_cs)
);

wire [23:0] vga_o;
wire vga_hs, vga_vs, vga_cs;
wire [23:0] vga_o, vga_o_t;
wire vga_hs, vga_vs, vga_cs, vga_hs_t, vga_vs_t, vga_cs_t;
vga_out vga_out
(
.clk(clk_vid),
.ypbpr_en(ypbpr_en),
.hsync(vga_hs_osd),
.vsync(vga_vs_osd),
.csync(vga_cs_osd),
.dout(vga_o),
.dout(vga_o_t),
.din(vga_data_osd),
.hsync_o(vga_hs),
.vsync_o(vga_vs),
.csync_o(vga_cs)
.hsync_o(vga_hs_t),
.vsync_o(vga_vs_t),
.csync_o(vga_cs_t)
);

`ifdef MISTER_ENABLE_YC
assign {vga_o, vga_hs, vga_vs, vga_cs } = ~yc_en ? {vga_o_t, vga_hs_t, vga_vs_t, vga_cs_t } : {yc_o, yc_hs, yc_vs, yc_cs };
`else
assign {vga_o, vga_hs, vga_vs, vga_cs } = {vga_o_t, vga_hs_t, vga_vs_t, vga_cs_t } ;
`endif

wire cs1 = (vga_fb | vga_scaler) ? vgas_cs : vga_cs;


assign VGA_VS = (VGA_EN | SW[3]) ? 1'bZ : (((vga_fb | vga_scaler) ? (~vgas_vs ^ VS[12]) : VGA_DISABLE ? 1'd1 : ~vga_vs) | csync_en);
assign VGA_HS = (VGA_EN | SW[3]) ? 1'bZ : ((vga_fb | vga_scaler) ? ((csync_en ? ~vgas_cs : ~vgas_hs) ^ HS[12]) : VGA_DISABLE ? 1'd1 : (csync_en ? ~vga_cs : ~vga_hs));
assign VGA_R = (VGA_EN | SW[3]) ? 6'bZZZZZZ : (vga_fb | vga_scaler) ? vgas_o[23:18] : VGA_DISABLE ? 6'd0 : vga_o[23:18];
assign VGA_G = (VGA_EN | SW[3]) ? 6'bZZZZZZ : (vga_fb | vga_scaler) ? vgas_o[15:10] : VGA_DISABLE ? 6'd0 : vga_o[15:10];
assign VGA_B = (VGA_EN | SW[3]) ? 6'bZZZZZZ : (vga_fb | vga_scaler) ? vgas_o[7:2] : VGA_DISABLE ? 6'd0 : vga_o[7:2] ;
`endif


`ifdef MISTER_ENABLE_YC
wire [23:0] yc_o;
wire yc_hs, yc_vs, yc_cs;
wire [39:0] PhaseInc;
yc_out yc_out
(
.clk(clk_vid),
.PAL_EN(pal_en),
.PHASE_INC(PhaseInc),
.COLORBURST_RANGE(COLORBURST_RANGE),
.hsync(vga_hs_osd),
.vsync(vga_vs_osd),
.csync(vga_cs_osd),
.dout(yc_o),
.din(vga_data_osd),
.hsync_o(yc_hs),
.vsync_o(yc_vs),
.csync_o(yc_cs)
);
`endif

reg video_sync = 0;
always @(posedge clk_vid) begin
reg [11:0] line_cnt = 0;
Expand Down Expand Up @@ -1567,6 +1604,12 @@ reg [1:0] sl_r;
wire [1:0] sl = sl_r;
always @(posedge clk_sys) sl_r <= FB_EN ? 2'b00 : scanlines;

`ifdef MISTER_ENABLE_YC
wire pal_en;
wire yc_en;
wire [26:0] COLORBURST_RANGE;
`endif

emu emu
(
.CLK_50M(FPGA_CLK2_50),
Expand All @@ -1592,7 +1635,12 @@ emu emu
.HDMI_WIDTH(direct_video ? 12'd0 : hdmi_width),
.HDMI_HEIGHT(direct_video ? 12'd0 : hdmi_height),
.HDMI_FREEZE(freeze),

`ifdef MISTER_ENABLE_YC
.COLORBURST_RANGE(COLORBURST_RANGE),
.PALFLAG(pal_en),
.YC_EN(yc_en),
.CHROMA_PHASE_INC(PhaseInc),
`endif
.CLK_VIDEO(clk_vid),
.CE_PIXEL(ce_pix),
.VGA_SL(scanlines),
Expand Down

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