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MortezaRezaalipour/README.md

Morteza Rezaalipour

FPGA/ASIC (Verilog/VHDL) Enthusiast | Low Power Approximate Computing | PhD candidate at USI | Part-time Teacher

As a PhD candidate in VLSI and computer architecture, I specialize in low-power circuit development for image and video processing and machine learning, focusing on approximate computing as a new computing paradigm. My background includes a strong research record and hands-on experience, notably with the University of Utah. Skilled in conveying complex ideas in native-level English, I am a fast learner, adaptable, dynamic, and motivated. With a positive outlook, I am keen to bring my expertise in approximate logic synthesis to the industry, applying my skills to address real-world challenges and drive technological progress.

LinkedIn       ReaserchGate       Google Scholar

🧰 Languages and Tools

Python

C/C++

MATLAB

Verilog

VHDL

Git

Linux

GitHub

Bash


📊 Stats

MortezaRezaalipour's Stats

Pinned

  1. JPEG_Encoder_VHDL JPEG_Encoder_VHDL Public

    A Simple JPEG Encoder in VHDL

    VHDL 2

  2. ErrorEval ErrorEval Public

    This is the open source code for our paper titled "ErrorEval: an Open-Source Worst-Case-Error Evaluation Framework for Approximate Computing"

    Verilog 3

  3. VerilogChecker VerilogChecker Public

    A circuit equivalence checker given an error threshold for Approximate Computing

    Python 2

  4. mohrez86/AxMAP mohrez86/AxMAP Public

    AxMAP: Making Approximate Adders Aware of Input Patterns

    MATLAB 1 2

  5. Synthesizable-VHDL-Implementation-of-Cyclic-Codes Synthesizable-VHDL-Implementation-of-Cyclic-Codes Public

    My BSc Project: Implementation & Evaluation of a cyclic code using FPGA

    VHDL 2

  6. VerilogPADAnalyzer VerilogPADAnalyzer Public

    VerilogPADAnalyzer is a Python application designed to analyze and report the Power, Area, and Delay (PAD) of Verilog input circuits.

    Python 2