Add optimized variant of CMN for HWC to HWC pad FP16 case #4993
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Signed-off-by: Krzysztof Lecki <klecki@nvidia.com>
Signed-off-by: Krzysztof Lecki <klecki@nvidia.com>
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awolant
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Introduce an optimized kernel for the HWC -> HWC, pad case for FP16. With current DALI allocation patterns, all outputs are aligned to multiple of 4, allowing to implement the output loop as writing pair of two lower channels, pair of two higher channels for each pixel using vectorized fp16 instructions, resulting in 4 byte accesses to output gmem. This yields up to 3x speedups compared to the previous version used by DALI for this particular case. There is a safety fallback in case if the memory is not actually aligned. Signed-off-by: Krzysztof Lecki <klecki@nvidia.com>
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Category: New feature, Refactoring
Description:
Introduce an optimized kernel for the HWC -> HWC, pad case for FP16.
With current DALI allocation patterns, all outputs are aligned to multiple of 4,
allowing to implement the output loop as writing pair of two lower channels, pair of two higher channels
for each pixel using vectorized fp16 instructions, resulting in 4 byte accesses to output gmem.
This yields up to 3x speedups compared to the previous version used by DALI for this particular case.
There is a safety fallback in case if the memory is not actually alinged.
Additional information:
Affected modules and functionalities:
CMN
Key points relevant for the review:
Tests:
This is already covered by existing tests, current implementation gets more specialized version
for one particular case.
Checklist
Documentation
DALI team only
Requirements
REQ IDs: N/A
JIRA TASK: N/A