Overview

This repository contains a collection of low-level modules extracted from various OpenROAD designs spanning different categories and PPA numbers generated by Yosys using area-optimized and delay-optimized synthesis recipes used in OpenROAD. The organization of this repostory is designed to help users easily navigate and locate specific design components.

Text file contains the json hierarchy of module instances in the top level module design including the path of low level modules (in the original OpenROAD directory structure, although the low level modules have been directly included in the design directory here for convenience)

Generate Synthesis Data using Yosys

1. There are three scripts: copy_low_level_modules_gen_synscript.py, run_synthesis_for_low_level_modules.py and collect_area_delay_synthesis.py.

2. Run python copy_low_level_modules_gen_synscript.py <path_to_RTL_dataset>. This will generate area-oriented and delay-oriented synthesis scripts for all leaf level RTL modules residing in openROAD_low_level_modules_yosys_v1.

3. Run python run_synthesis_for_low_level_modules.py <path_to_RTL_dataset>. This will perform logic synthesis using Yosys. The synthesis status gets dumped in <path_to_RTL_dataset>/synthesis_designs/synthesis_status.csv. The yosys logs are dumped in <path_to_RTL_dataset>/dump.

4. Run python collect_area_delay_synthesis.py <path_to_RTL_dataset>. This will generate <path_to_RTL_dataset>/dump/synthesis_data_nangate45nm.csv file having labeled data of yosys synthesized with area-oriented and delay-oriented recipes.

Folder Structure

• openROAD_low_level_modules_yosys_v1
  • intel16
    • aes
      • aes_cipher_top_design_hierarchy.txt
      • aes_rcon.v
      • aes_sbox.v
    • gcd
      • gcd_design_hierarchy.txt
      • RegRst_0x9f365fdf6c8998a.v
      • LtComparator_0x422b1f52edd46a85.v
      • GcdUnitDpathRTL_0x4d0fc71ead8d3d9e.v
      • Subtractor_0x422b1f52edd46a85.v
      • Mux_0x683fa1a418b072c9.v
      • RegEn_0x68db79c4ec1d6e5b.v
      • ZeroComparator_0x422b1f52edd46a85.v
    • ...
  • gf55

    • aes

      • aes_cipher_top_design_hierarchy.txt
      • aes_rcon.v
      • aes_sbox.v

    • ...

  • ...

This structured arrangement allows for easy access to design categories and their respective sub-categories, along with the associated design hierarchy and low-level modules. Users can quickly locate and work with specific design elements as needed.