Skip to content

The project involves designing a Simple RISC Computer (SRC) processor with 23 instructions, 32 registers, a control unit, data path, and memory components, aiming to create a functional CPU architecture capable of executing instructions.

License

Notifications You must be signed in to change notification settings

NajimAlfutini/Design-A-Full-SRC-Processor

Folders and files

NameName
Last commit message
Last commit date

Latest commit

 

History

11 Commits
 
 
 
 
 
 
 
 
 
 

Repository files navigation

Design A Full SRC Processor

A SRC (Simple RISC Computer) processor is a type of computer processor that uses a limited number of instructions to perform its tasks. RISC processors are widely used in a variety of applications, including embedded systems, mobile devices, and servers. They are known for their high performance and low power consumption, making them an attractive choice for many types of systems.

RISC processors are designed to be simple, fast, and efficient, with a focus on executing a small set of instructions fast rather than trying to support many complex instructions.

Processor specs and design logic (Design Decisions):

SRC processor has specific specifications, the specs of the SRC that we designed is:

Our design is a 1-bus system. Which means we use one bus to transmit/share data between the components.
In every clock we perform one micro-operation.
It has a 32 general purpose register and each one has size of 32-bit .
It has a 32-bit program counter (PC) which means it can access 2^32 = 4GB.
It has a 32-bit instruction register (IR).
The word is 4 bytes = 32-bit, and only a 4 byte can be fetched or stored into main memory.
Main memory is organized as an array of bytes.

image

The control unit design:

image

The control unit contains of four main components:

  1. Clocking logic: The main function of this component is to generate enable signal for the counter in the step generator. image

  2. The control step generator: contains of a four-bit up counter and control step decoder which give the wanted step. The counter is with load input because if the counter reserve a Goto6 signal must the step generator go to step 6 by load 0110 to counter. image

  3. Opcode decoder: This decoder will take opcode as input IR<31 …27> and will generate a signal in the wanted instruction.

  4. Control signal encoder: Is the main part in control unit because it contains a Boolean function for each signal.

This is all the signals that has Boolean function:
Boolean Functions

About

The project involves designing a Simple RISC Computer (SRC) processor with 23 instructions, 32 registers, a control unit, data path, and memory components, aiming to create a functional CPU architecture capable of executing instructions.

Topics

Resources

License

Stars

Watchers

Forks

Releases

No releases published

Packages

No packages published

Languages