fix instruction cache issue

NakajoLab · Mar 28, 2024 · 8fb389f · 8fb389f
1 parent f97b596
commit 8fb389f
Show file tree

Hide file tree

Showing 10 changed files with 38,356 additions and 26,332 deletions.
diff --git a/b4smt/src/main/scala/b4smt/B4SMTCore.scala b/b4smt/src/main/scala/b4smt/B4SMTCore.scala
@@ -335,7 +335,10 @@ object B4SMTCore extends App {
     new B4SMTCoreFixedPorts(),
     Array.empty,
     Array(
-      "--lowering-options=disallowLocalVariables,disallowPackedArrays,noAlwaysComb",
+//      "--lowering-options=disallowLocalVariables,disallowPackedArrays,noAlwaysComb",
+      "-O=release",
+      "--emit-omir",
+      "--export-module-hierarchy",
       "--disable-all-randomization",
       "--add-vivado-ram-address-conflict-synthesis-bug-workaround",
     ),

diff --git a/b4smt/src/main/scala/b4smt/modules/cache/CacheFetchInterface.scala b/b4smt/src/main/scala/b4smt/modules/cache/CacheFetchInterface.scala
@@ -5,6 +5,25 @@ import chisel3.util._
 import _root_.circt.stage.ChiselStage
 import b4smt.Parameters
 import b4smt.connections.InstructionCache2Fetch
+import b4smt.utils.ShiftRegister
+
+// strategy memo
+// a,f,edge
+//
+//cases of return
+//!edge a=f
+//edge a'=f a=f+1
+//
+//fetching
+//!edge
+//    a != f
+//		fetch a <- f
+//edge
+//    !(a'=f & a=f+1)
+//		a = f
+//			fetch a <- f + 1
+//		otherwise
+//			fetch a <- f
 
 class CacheFetchInterface(implicit params: Parameters) extends Module {
   val io = IO(new Bundle {
@@ -26,18 +45,14 @@ class CacheFetchInterface(implicit params: Parameters) extends Module {
     io.fetch.requestNext.ready := true.B
   }
 
-  val fetchedAddressValid = RegInit(false.B)
-  val fetchedAddress = RegInit("xFFFFFFFF_FFFFFFFF".U)
-  val fetchedAddressNow = WireDefault(fetchedAddress)
+  val fetchedAddressValid = RegInit(true.B)
+  val fetchedAddressSR = ShiftRegister(UInt(64.W), 2, "xFFFFFFFF_FFFFFFFF".U)
   val fetchedData = Reg(UInt(128.W))
   val prevFetchedDataTop16 = Reg(UInt(16.W))
-  val nextBlock = RegInit(false.B)
 
   val requestingAddress = io.fetch.perDecoder(0).request.bits
   val requestingAddressValid = io.fetch.perDecoder(0).request.valid
 
-  val fetchNew = RegInit(true.B)
-  val fetchNewNow = WireDefault(fetchNew)
   val isEdge = requestingAddress(3, 0) === BitPat("b111?")
   val isRequesting = RegInit(false.B)
 
@@ -47,54 +62,45 @@ class CacheFetchInterface(implicit params: Parameters) extends Module {
     isRequesting := false.B
   }
 
-  when(
-    requestingAddressValid &&
-      (fetchedAddress(63, 4) =/=
-        requestingAddress(63, 4) || isEdge),
-  ) {
-    fetchNewNow := true.B
-  }
-
-  when(requestingAddressValid && fetchNewNow) {
-
-    when(isEdge) {
-      when(
-        fetchedAddress(63, 4) === requestingAddress(63, 4)
-          && fetchedAddressValid,
-      ) {
-        // 　端のアドレスかつ、現在のアドレスのデータの取得が完了している。
+  when(requestingAddressValid && fetchedAddressValid) {
 
+    when(!isEdge) {
+      when(fetchedAddressSR.output(0)(63, 4) =/= requestingAddress(63, 4)) {
         io.cache.request.valid := true.B
         io.cache.request.bits :=
-          (requestingAddress(63, 4) + 1.U) ## 0.U(4.W)
+          requestingAddress(63, 4) ## 0.U(4.W)
         when(io.cache.request.ready) {
-          fetchedAddress := (requestingAddress(63, 4) + 1.U) ## 0.U(4.W)
+          fetchedAddressSR.shift(requestingAddress(63, 4) ## 0.U(4.W))
           fetchedAddressValid := false.B
-          fetchNew := false.B
-          nextBlock := true.B
           prevFetchedDataTop16 := fetchedData(127, 112) // top 16 bits
         }
-      }.elsewhen(fetchedAddress(63, 4) === requestingAddress(63, 4) + 1.U) {
-        // 何もしない
-      }.otherwise {
-        // 端のアドレスででだが直前に取得したアドレスが現在以外
-        io.cache.request.valid := true.B
-        io.cache.request.bits := requestingAddress(63, 4) ## 0.U(4.W)
-        when(io.cache.request.ready) {
-          fetchedAddress := requestingAddress(63, 4) ## 0.U(4.W)
-          fetchedAddressValid := false.B
-          fetchNew := isEdge
-          nextBlock := false.B
-        }
       }
     }.otherwise {
-      io.cache.request.valid := true.B
-      io.cache.request.bits := requestingAddress(63, 4) ## 0.U(4.W)
-      when(io.cache.request.ready) {
-        fetchedAddress := requestingAddress(63, 4) ## 0.U(4.W)
-        fetchedAddressValid := false.B
-        fetchNew := isEdge
-        nextBlock := (requestingAddress(63, 4) - fetchedAddress) === 1.U
+      when(
+        !(fetchedAddressSR.output(1)(63, 4) ===
+          requestingAddress(63, 4) &&
+          fetchedAddressSR.output(0)(63, 4) ===
+          (requestingAddress(63, 4) + 1.U)),
+      ) {
+        when(fetchedAddressSR.output(0)(63, 4) === requestingAddress(63, 4)) {
+          io.cache.request.valid := true.B
+          io.cache.request.bits :=
+            (requestingAddress(63, 4) + 1.U) ## 0.U(4.W)
+          when(io.cache.request.ready) {
+            fetchedAddressSR.shift((requestingAddress(63, 4) + 1.U) ## 0.U(4.W))
+            fetchedAddressValid := false.B
+            prevFetchedDataTop16 := fetchedData(127, 112) // top 16 bits
+          }
+        }.otherwise {
+          io.cache.request.valid := true.B
+          io.cache.request.bits :=
+            requestingAddress(63, 4) ## 0.U(4.W)
+          when(io.cache.request.ready) {
+            fetchedAddressSR.shift(requestingAddress(63, 4) ## 0.U(4.W))
+            fetchedAddressValid := false.B
+            prevFetchedDataTop16 := fetchedData(127, 112) // top 16 bits
+          }
+        }
       }
     }
   }
@@ -113,23 +119,25 @@ class CacheFetchInterface(implicit params: Parameters) extends Module {
   // fetch response
   when(fetchedAddressValidNow) {
     io.fetch.perDecoder foreach { f =>
-      f.response.bits := MuxLookup(f.request.bits(3, 1), 0.U)(
-        (0 until 8 - 1).map(i => i.U -> fetchedDataNow(16 * i + 32 - 1, 16 * i)),
-      )
       when(f.request.valid) {
-        when((f.request.bits(63, 4) + 1.U) === fetchedAddressNow(63, 4)) {
-          when(f.request.bits(3, 0) === BitPat("b111?") && nextBlock) {
+        when(f.request.bits(3, 0) === BitPat("b111?")) {
+          when(
+            f.request.bits(63, 4) ===
+              fetchedAddressSR.output(1)(63, 4) &&
+              (f.request.bits(63, 4) + 1.U) ===
+              fetchedAddressSR.output(0)(63, 4),
+          ) {
             f.response.valid := true.B
             f.response.bits := fetchedDataNow(15, 0) ## prevFetchedDataTop16
-          }.otherwise {
-            f.response.valid := false.B
           }
-        }
-        when(f.request.bits(63, 4) === fetchedAddressNow(63, 4)) {
-          when(f.request.bits(3, 0) === BitPat("b111?")) {
-            f.response.valid := false.B
-          }.otherwise {
+        }.otherwise {
+          when(f.request.bits(63, 4) === fetchedAddressSR.output(0)(63, 4)) {
             f.response.valid := true.B
+            f.response.bits := MuxLookup(f.request.bits(3, 1), 0.U)(
+              (0 until 8 - 1).map(i =>
+                i.U -> fetchedDataNow(16 * i + 32 - 1, 16 * i),
+              ),
+            )
           }
         }
       }

diff --git a/b4smt/src/main/scala/b4smt/modules/csr/CSR.scala b/b4smt/src/main/scala/b4smt/modules/csr/CSR.scala
@@ -160,6 +160,14 @@ class CSR(implicit params: Parameters) extends Module with FormalTools {
       io.CSROutput.bits.value := atomicFullCount
     }.elsewhen(address === CSRs.hpmcounter15.U) {
       io.CSROutput.bits.value := reservationStationFullCount
+    }.elsewhen(address === CSRs.misa.U) {
+      io.CSROutput.bits.value := MisaGen()
+    }.elsewhen(address === CSRs.mvendorid.U) {
+      io.CSROutput.bits.value := 0.U
+    }.elsewhen(address === CSRs.marchid.U) {
+      io.CSROutput.bits.value := 0.U
+    }.elsewhen(address === CSRs.mimpid.U) {
+      io.CSROutput.bits.value := 0.U
     }.elsewhen(address === CSRCustom.coreCount.U) {
       io.CSROutput.bits.value := params.threads.U
     }.elsewhen(address === CSRCustom.customInt.U) {

diff --git a/b4smt/src/main/scala/b4smt/modules/csr/MisaGen.scala b/b4smt/src/main/scala/b4smt/modules/csr/MisaGen.scala
@@ -0,0 +1,13 @@
+package b4smt.modules.csr
+
+import chisel3._
+
+object MisaGen {
+  def apply(): UInt = {
+    val bits =
+      // XX: MXL
+      // XX000000000000000000000000000000000000ZYXWVUTSRQPONMLKJIHGFEDCBA
+      "b_1000000000000000000000000000000000000000000000001000000100000101".U
+    bits
+  }
+}
diff --git a/b4smt/src/main/scala/b4smt/utils/ShiftRegister.scala b/b4smt/src/main/scala/b4smt/utils/ShiftRegister.scala
@@ -0,0 +1,39 @@
+package b4smt.utils
+
+import chisel3._
+import chisel3.util._
+import _root_.circt.stage.ChiselStage
+
+class ShiftRegister[T <: Data](t: T, width: Int, init: T) extends Module {
+  val input = IO(Flipped(Valid(t)))
+  val output = IO(Vec(width, t))
+
+  val registers = RegInit(VecInit(Seq.fill(width)(init)))
+
+  when(input.valid) {
+    for (i <- 1 until width) {
+      registers(i) := registers(i - 1)
+    }
+    registers(0) := input.bits
+  }
+
+  output := registers
+
+  def shift(data: T): Unit = {
+    input.valid := true.B
+    input.bits := data
+  }
+}
+
+object ShiftRegister extends App {
+  ChiselStage.emitSystemVerilogFile(new ShiftRegister(UInt(32.W), 5, 0.U))
+
+  def apply[T <: Data](t: T, width: Int, init: T): ShiftRegister[T] = {
+    val m = Module(new ShiftRegister(t, width, init))
+    m.input.valid := false.B
+    m.input.bits := 0.U.asTypeOf(t)
+    m
+  }
+  def apply[T <: Data](t: T, width: Int):ShiftRegister[T] = ShiftRegister(t, width, 0.U.asTypeOf(t))
+
+}
diff --git a/b4smt/src/test/scala/b4smt/B4SMT_Full_Tests/B4SMTCoreProgramTest.scala b/b4smt/src/test/scala/b4smt/B4SMT_Full_Tests/B4SMTCoreProgramTest.scala
@@ -639,7 +639,7 @@ class B4SMTCoreProgramTest extends AnyFlatSpec with ChiselScalatestTester {
       }
   }
 
-  ignore should "run testhex" taggedAs Slow in {
+  it should "run testhex" taggedAs Slow in {
     test(
       new B4SMTCoreWithMemory()(
         defaultParams.copy(
@@ -657,7 +657,7 @@ class B4SMTCoreProgramTest extends AnyFlatSpec with ChiselScalatestTester {
     )
       .withAnnotations(
         Seq(
-//          WriteWaveformAnnotation,
+          WriteWaveformAnnotation,
           VerilatorBackendAnnotation,
           CachingAnnotation,
         ),

diff --git a/flake.lock b/flake.lock
diff --git a/pext/src/main/scala/b4smt_pext/PExtExecutor.scala b/pext/src/main/scala/b4smt_pext/PExtExecutor.scala
@@ -32,6 +32,7 @@ import PExtMisc2.pextMisc2
 import PExtQ16Saturate.pextQ16Saturate
 import PExtQ32Saturate.pextQ32Saturate
 import PExtSigned16MulWith32AddSub.pextSigned16MulWith32AddSub
+import PExtSigned16MulWith64AddSub.pextSigned16MulWith64AddSub
 import chisel3._
 import chisel3.util._
 
@@ -73,7 +74,7 @@ class PExtExecutor extends Module {
       pextMsw32x32(io.input.rs1, io.input.rs2, io.input.rd) ++
       pextMsw32x16(io.input.rs1, io.input.rs2, io.input.rd) ++
       pextSigned16MulWith32AddSub(io.input.rs1, io.input.rs2, io.input.rd) ++
-//    pextSigned16MulWith64AddSub(io.input.rs1,io.input.rs2) ++
+      pextSigned16MulWith64AddSub(io.input.rs1, io.input.rs2, io.input.rd) ++
       pextMisc(io.input.rs1, io.input.rs2, io.input.rd, io.input.imm) ++
       pext8MulWith32Add(
         io.input.rs1,

diff --git a/pext/src/main/scala/b4smt_pext/PExtSigned16MulWith64AddSub.scala b/pext/src/main/scala/b4smt_pext/PExtSigned16MulWith64AddSub.scala
@@ -5,7 +5,7 @@ import PExtensionOperation._
 import UIntSectionHelper._
 
 object PExtSigned16MulWith64AddSub {
-  def pextSigned16MulWith32AddSub(rs1: UInt, rs2: UInt, rd: UInt) = {
+  def pextSigned16MulWith64AddSub(rs1: UInt, rs2: UInt, rd: UInt) = {
     def SMALXX(fst: Boolean, snd: Boolean) = {
       val m0 = rs1.W(0).H(if (fst) 1 else 0).asSInt * rs2
         .W(0)