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Original file line number | Diff line number | Diff line change |
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package b4smt.modules.csr | ||
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import chisel3._ | ||
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object MisaGen { | ||
def apply(): UInt = { | ||
val bits = | ||
// XX: MXL | ||
// XX000000000000000000000000000000000000ZYXWVUTSRQPONMLKJIHGFEDCBA | ||
"b_1000000000000000000000000000000000000000000000001000000100000101".U | ||
bits | ||
} | ||
} |
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Original file line number | Diff line number | Diff line change |
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package b4smt.utils | ||
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import chisel3._ | ||
import chisel3.util._ | ||
import _root_.circt.stage.ChiselStage | ||
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class ShiftRegister[T <: Data](t: T, width: Int, init: T) extends Module { | ||
val input = IO(Flipped(Valid(t))) | ||
val output = IO(Vec(width, t)) | ||
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val registers = RegInit(VecInit(Seq.fill(width)(init))) | ||
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when(input.valid) { | ||
for (i <- 1 until width) { | ||
registers(i) := registers(i - 1) | ||
} | ||
registers(0) := input.bits | ||
} | ||
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output := registers | ||
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def shift(data: T): Unit = { | ||
input.valid := true.B | ||
input.bits := data | ||
} | ||
} | ||
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object ShiftRegister extends App { | ||
ChiselStage.emitSystemVerilogFile(new ShiftRegister(UInt(32.W), 5, 0.U)) | ||
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def apply[T <: Data](t: T, width: Int, init: T): ShiftRegister[T] = { | ||
val m = Module(new ShiftRegister(t, width, init)) | ||
m.input.valid := false.B | ||
m.input.bits := 0.U.asTypeOf(t) | ||
m | ||
} | ||
def apply[T <: Data](t: T, width: Int):ShiftRegister[T] = ShiftRegister(t, width, 0.U.asTypeOf(t)) | ||
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} |
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